SY69952

Micrel-Synergy's SY69952 contains fully integrated transmitter and receiver functions designed to provide clock recovery and generation for either 51.84Mbit/s OC/ STS-1 or 155.52Mbit/s OC/STS-3 SONET/SDH (SY69952) and ATM applications.

On-chip clock generation is performed by a low-jitter phase-locked loop (PLL) allowing use of 19.44MHz reference for 155.52MHz generation or a 6.48MHz reference for 51.84MHz generation. Clock recovery is performed by synchronizing the on-chip VCO directly to the incoming data stream. The SY69952 meets the jitter compliance criteria of Bellcore, ITU/CCITT and ANSI standards. Low jitter is ensured by Micrel-Synergy's advanced PLL technology and positive ECL (PECL) I/O.Micrel-Synergy's circuit design techniques coupled with ASSET™ bipolar technology result in ultra-fast performance with low noise and low power dissipation.