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SH7144F-ZTAT

Features: • Central processing unit with an internal 32-bit RISC (Reduced Instruction Set Computer) architecture Instruction length: 16-bit fixed length for improved code efficiency Load-store architecture (basic operations are executed between registers) Sixteen 32-b...

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SeekIC No. : 004489616 Detail

SH7144F-ZTAT: Features: • Central processing unit with an internal 32-bit RISC (Reduced Instruction Set Computer) architecture Instruction length: 16-bit fixed length for improved code efficiency...

SH7144F-ZTAT Data Sheet

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Part Number:
SH7144F-ZTAT
Supply Ability:
5000

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  • 1~5000
  • Unit Price
  • Negotiable
  • Processing time
  • 15 Days
Total Cost: $ 0.00

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Upload time: 2024/11/21

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Product Details

Description



Features:

• Central processing unit with an internal 32-bit RISC (Reduced Instruction Set Computer) architecture
 Instruction length: 16-bit fixed length for improved code efficiency
 Load-store architecture (basic operations are executed between registers)
 Sixteen 32-bit general registers
 Five-stage pipeline
 On-chip multiplier: multiplication operations (32 bits * 32 bits 64 bits) executed in two to four cycles
 C language-oriented 62 basic instructions
• Various peripheral functions
 Direct memory access controller (DMAC)
 Data transfer controller (DTC)


Pinout

Connection Diagram


Specifications

Item
Symbol
Rating
Unit
Power supply voltage
VCC
0.3 to +4.3
V
Input voltage All pins other than analog input pins
Vin
0.3 to VCC +0.3
V
Analog input pins
Vin
0.3 to AVCC +0.3
V
Analog supply voltage
AVCC
0.3 to +4.3
V
Analog reference voltage (Only in SH7145)
VAref
0.3 to AVCC +0.3
V
Analog input voltage
VAN
0.3 to AVCC +0.3
V
Operating temperature (except programming or
erasing flash memory)		 Regular specifications
Topr
20 to +75
°C
Wide range specifications
40 to +85
°C
Operating temperature
(programming or erasing flash memory)
TWEopr
20 to +75
°C
Storage temperature
Tstg
55 to +125
°C



Description

The UBC has the following registers. For details on register addresses and register states during each processing, refer to section 25, List of Registers.
• User break address register H (UBARH)
• User break address register L (UBARL)
• User break address mask register H (UBAMRH)
• User break address mask register L (UBAMRL)
• User break bus cycle register (UBBR)
• User break control register (UBCR)




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