S3014

The function of the S3014 clock synthesis and recovery unit is to derive high speed timing signals for SONET/SDH-based equipment. The S3014 is implemented using AMCC's proven Phase Locked Loop (PLL) technology.

In Clock Recovery mode, the S3014 receives either an STS-3/STM-1 or STS-12/STM-4 scrambled NRZ signal and recovers the clock from the data. The chip outputs a differential ECL bit clock and retimed data. In Clock Synthesis mode, the S3014 receives a 19.44, 51.84, or 155.52 MHz reference clock and outputs an STS-3/STM-1 or STS-12/STM-4 differential ECL clock.

The S3014 utilizes an on-chip PLL which consists of a phase detector, a loop filter, and a voltage controlled oscillator (VCO). The phase detector compares the phase relationship between the VCO output and the REFCLK input, a loop filter converts the phase detector output into a smooth DC voltage, and the DC voltage of S3014 is input to the VCO whose frequency is varied by this voltage. A block diagram is shown in Figure 1.