S2204

Features: • 1250 MHz (Gigabit Ethernet) operating rate - 1/2 Rate Operation• IEEE 802.3z Gigabit Ethernet Compatible• Quad Transmitter with phase-locked loop (PLL) clock synthesis from low speed reference• Quad Receiver PLL provides clock and data recovery• Internally...

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S2204 Picture
SeekIC No. : 004481628 Detail

S2204: Features: • 1250 MHz (Gigabit Ethernet) operating rate - 1/2 Rate Operation• IEEE 802.3z Gigabit Ethernet Compatible• Quad Transmitter with phase-locked loop (PLL) clock synthesis ...

floor Price/Ceiling Price

Part Number:
S2204
Supply Ability:
5000

Price Break

  • Qty
  • 1~5000
  • Unit Price
  • Negotiable
  • Processing time
  • 15 Days
Total Cost: $ 0.00

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Upload time: 2024/11/22

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Product Details

Description



Features:

• 1250 MHz (Gigabit Ethernet) operating rate - 1/2 Rate Operation
• IEEE 802.3z Gigabit Ethernet Compatible
• Quad Transmitter with phase-locked loop (PLL) clock synthesis from low speed reference
• Quad Receiver PLL provides clock and data recovery
• Internally series terminated TTL outputs
• Low-jitter serial PECL interface
• Individual local loopback control
• JTAG 1149.1 Boundary scan on low speed I/O signals
• Interfaces with coax, twinax, or fiber optics
• Single +3.3V supply, 2.5 W power dissipation
• Compact 23mm x 23mm 208 TBGA package



Application

• Ethernet Backbones
• Workstation
• Frame buffer
• Switched networks
• Data broadcast environments
• Proprietary extended backplanes



Specifications

Parameter

Min

Typ

Max

Units

Storage Temperature

-65

 

150

° C

Voltage on VDD with Respect to GND

-0.5

 

+5.0

V

Voltage on any TTL Input Pin

-0.5

 

3.47

V

Voltage on any PECL Input Pin

0

 

VDD

V

TTL Output Sink Current

 

 

8

mA

TTL Output Source Current  

 

8

mA

High Speed PECL Output Source Current

 

 

25

mA

ESD Sensitivity 1

Over 500 V

1. Human body model.


Description

The S2204 facilitates high-speed serial transmission of data in a variety of applications including Gigabit Ethernet, serial backplanes, and proprietary point to point links. The chip provides four separate transceivers which can be operated individually for a data capacity of >4 Gbps.

Each bi-directional channel provides parallel to serial and serial to parallel conversion, clock generation/ recovery, and framing. The on-chip transmit PLL synthesizes the high-speed clock from a low-speed reference. The on-chip quad receive PLL is used for clock recovery and data re-timing on the four independent data inputs. The transmitter and receiver each support differential PECL-compatible I/O for copper or fiber optic component interfaces with excellent signal integrity. Local loopback mode allows for system diagnostics. The chip requires a 3.3V power supply and dissipates 2.5 watts.

Figure 1 shows the S2204 and S2004 in a Gigabit Ethernet application. Figure 2 combines the S2204 with a crosspoint switch to demonstrate a serial backplane application. Figure 3 is the input/ output diagram. Figures 4 and 5 show the transmit and receive block diagrams, respectively.

 




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