Features: • 1.8 V ± 0.1 V power supply for core (VDD)
• 1.4 V to VDD power supply for I/O (VDDQ)
• DLL circuitry for wide output data valid window and future frequency scaling
• Separate independent read and write data ports with concurrent transactions
• 100% bus utilization DDR read and write operation
• Four-tick burst for reduced address frequency
• Two input clocks (K and /K) for precise DDR timing at clock rising edges only
• Two output clocks (C and /C) for precise flight time and clock skew matching-clock and data delivered together to
receiving device
• Internally self-timed write control
• Clock-stop capability with µs restart
• User programmable impedance output
• Fast clock cycle time: 3.0 ns (333 MHz)/3.3 ns (300 MHz)/4.0 ns (250 MHz)/
5.0 ns (200 MHz)/6.0 ns (167 MHz)
• Simple control logic for easy depth expansion
• JTAG boundary scanSpecifications
|
Parameter |
Symbol |
Rating |
Unit |
Notes |
| Input voltage on any ball |
VIN |
−0.5 to VDD + 0.5 (2.5 V max.) |
V |
1,4 |
| Input/output voltage |
VI/O |
−0.5 to VDDQ + 0.5 (2.5 V max.) |
V |
1,4 |
| Core supply voltage |
VDD |
−0.5 to 2.5 |
V |
1,4 |
| Output supply voltage |
VDDQ |
−0.5 to VDD |
V |
1,4 |
| Junction temperature |
Tj |
+125 (max) |
°C |
|
| Storage temperature |
TSTG |
−55 to +125 |
°C |
|
Notes: 1. All voltage is referenced to VSS.
2. Permanent device damage may occur if Absolute Maximum Ratings are exceeded. Functional operation should be restricted the Operation Conditions. Exposure to higher than recommended voltages for extended periods of time could affect device reliability.
3. These CMOS memory circuits have been designed to meet the DC and AC specifications shown in the tables
after thermal equilibrium has been established.
4. The following supply voltage application sequence is recommended: VSS, VDD, VDDQ, VREF then VIN. Remember, according to the Absolute Maximum Ratings table, VDDQ is not to exceed 2.5 V, whatever the instantaneous value of VDDQ.
DescriptionThe R1Q3A3636 is a 1,048,576-word by 36-bit, the R1Q3A3618 is a 2,097,152-word by 18-bit, and the R1Q3A3609 is a 4,194,304-word by 9-bit synchronous quad data rate static RAM fabricated with advanced CMOS technology using full CMOS six-transistor memory cell. R1Q3A3618 integrates unique synchronous peripheral circuitry and a burst counter. All input registers controlled by an input clock pair (K and /K) and are latched on the positive edge of K and /K. The R1Q3A3618 is suitable for applications which require synchronous operation, high speed, low voltage, high density and
wide bit configuration. These products are packaged in 165-pin plastic FBGA package.
R1Q3A3618 Data Sheet
