QS5LV931-50Q

The QS5LV931-50Q clock driver uses an internal phase locked loop to lock low skew outputs to a reference clock input.Six outputs are available:Q0-Q4,Q/2.The QS5LV931-50Q includes an internal RC filter which provides excellent jitter characteristics and elimimates the need for external components.

Features of the QS5LV931-50Q are:(1)3.3V operation;(2)JEDEC LVTTL compatible level;(3)clock input is 5V tolerant;(4)Q outputs,Q/2 output;(5)<300ps output skew,Q0-Q4;(6)output 3-state and reset while OE/RST low;(7)PLL disable freature for low frequency testing;(8)internal loop filter RC network;(9)internal VCO/2 option;(10)balanced drive outputs ±24mA;(11)ESD>2000V;(12)80MHz maximum frequency;(13)available in QSOP package.

The absolute maximum ratings of the QS5LV931-50Q can be summarized as:(1):the symbol is AVDD/VDD,the parameter is supply voltage to ground,the Max is -0.5 to +7,the unit is V;(2):the parameter is DC input voltage VIN,the Max is -0.5 to +5.5,the unit is V;(3):the parameter is maximum power dissipation,the Max is 0.5,the unit is W;(4):the symbol is Tstg,the parameter is storage temperature,the Max is -65 to +150,the unit is .