QL7100

Clock Network
• 9 global clock networks
• 1 dedicated, 8 programmable
• 16 I/O (high drive) networks: Programmable I/O
• High performance enhanced I/O: less than 3 ns Tco
• Programmable slew rate control
• Programmable I/O standards
• LVTTL, LVCMOS, PCI, GTL+, SSTL2, and SSTL3
• 8 independent I/O banks
• 3 register configuration: Input, Output, OE2 banks per I/O
• 20 Quad-net networks: 5 per quadrant
Parameterized IP
• Free parameterized IP administered with a DSP Wizard
• Supports multiple and hierarchical IP instantiations
High Speed Customizable Logic
• 0.25u, 5 layer metal CMOS process
• 2.5 V Vcc, 2.5 / 3.3 V drive capable I/O
• 256 programmable I/O
• 960 Logic Cells
• 292,000 max system gates
• Muxed based architecture, non-volatile technology
• Completely customizable for any digital applications
Dual Port SRAM
• 36 blocks of dual-port SRAM
• 2,304 bit dual port high performance SRAM Blocks
• Total of 82,900 bits
• RAM / ROM / FIFO Wizard for automatic configuration
• Configurable and cascadable
• Array sizes of 2, 4, 9, and 18
• < 3 ns access times, 300+ MHz FIFO