PSD4XX

The PSD4XX family is a microcontroller peripheral that integrates high-performance and user-configurable blocks of EPROM, programmable logic, and SRAM into one part. The products also provide a powerful microcontroller interface that eliminates theneed for external "glue logic". The no "glue logic" concept provides a user-programmable interface to a variety of 8- and 16-bit (multiplexed or non-multiplexed) microcontrollers thatis easy to use. The part's integration, small form factor, low power consumption, and ease of use make it the ideal part for interfacing to virtually any microcontroller.

The PSD4XX provides two Zero-power PLDs (ZPLD): a Decode PLD (DPLD) and a General-purpose PLD (GPLD). A configuration bit (Turbo) can be set by the MCU, and will utomatically place the ZPLDs into Standby Mode if no inputs are changing. The ZPLDs are designed to consume minimum power using Zero-power CMOS technology that uses only 10 A (typical) standby current. Unused product terms are automatically disabled, also reducing power, regardless of the Turbo bit setting.

The main function of the DPLD is to perform address decoding for the internal I/O ports, EPROM, and SRAM. The PSD4XX address decoding can be based on up to 24 bits of address inputs, control signals (RD, WR, PSEN, etc.), and internal page logic. The DPLD supports separate program and data spaces (for 8031 compatible MCUs).

The PSD4XX General-purpose PLD (GPLD) can be used to implement various logic functions defined by the user, such as:
• State machines
• Loadable counters and shift registers
• Inter-processor mailbox
• External control logic (chip selects, output enables, etc.).
The GPLD has access to up to 59 inputs, 118 product terms, 24 macrocells, and 24 I/O pins.

The PSD4XX has 40 I/O pins that are divided among 5 ports. Each I/O pin can be
individually configured to provide many functions, including the following:
• MCU I/O
• GPLD I/O
• Latched address output (for MCUs with multiplexed data bus)
• Data bus (for MCUs with non-multiplexed data bus).

The PSD4XX can easily interface with virtually any 8- or 16-bit microcontroller with a multiplexed or non-multiplexed bus. All of the MCU control signals are connected to the ZPLDs, enabling the user to generate signals for external devices.

The PSD4XX provides between 256 Kbits and 1 Mbit of EPROM that is divided in to four equal-sized blocks. Each block can occupy a different address location, allowing for versatile address mapping. The access time of the EPROM includes the address latching and DPLD decoding.

The PSD4XX has an optional 16 Kbit SRAM that can be battery-backed by connecting a battery to the Vstby pin. The battery will protect the contents of the SRAM in the event of a power failure. Therefore, you can place data in the SRAM that you want to keep after the power is switched off. Power switchover to the battery automatically occurs when VCC drops below Vstby.

A four-bit Page Register enables easy access to the I/O section, EPROM, and SRAM PSD4XX for microcontrollers with limited address space. The Page Register outputs are connected to both ZPLDs and thus can also be used for external paging schemes.

The Power Management Unit (PMU) of the PSD4XX enables the user to control thepower consumption on selected functional blocks, based on system requirements. For microcontrollers that do not generate a chip select input for the PSD, the Automatic Power-Down (APD) unit of the PMU can be setup to enable the PSD to enter Power Down Mode or Sleep Mode, based on the inactivity of ALE (or AS).

Implementing your design has never been easier than with PSDsoft-ST's software development suite. Using PSDsoft, you can do the following:

• Configure your PSD4XX to work with virtually any microcontroller
• Specify what you want implemented in the programmable logic using a design file
• Simulate your design
• Download your design to the part using a programmer.