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Features: ❏ A simple interface to 16-bit microcontrollers that use either multiplexed or non-multiplexed busses. The bus interface logic uses the control signals generated by the microcontroller automatically when the address is decoded and a read or write is performed. A partial list of ...

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PSD4000: Features: ❏ A simple interface to 16-bit microcontrollers that use either multiplexed or non-multiplexed busses. The bus interface logic uses the control signals generated by the microcontr...

PSD4000 Data Sheet

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Part Number:: PSD4000
Supply Ability:: 5000

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1~5000

Unit Price
Negotiable

Processing time
15 Days

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Upload time: 2024/12/21

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Product Details

Description

Features:

❏ A simple interface to 16-bit microcontrollers that use either multiplexed
   or non-multiplexed busses. The bus interface logic uses the control signals
   generated by the microcontroller automatically when the address is decoded
and a read or write is performed. A partial list of the MCU families supported include:
    • Intel 80196, 80186, and 80386EX
    • Motorola 68HC16, 68HC12, 683XX, and MC2001
    • Philips 80C51XA
    • Infineon C16X devices
    • Hitachi H8
❏ 4 Mbit Flash memory. This is the main Flash memory. It is divided into eight
    equal-sized blocks that can be accessed with user-specified addresses.
❏ Internal secondary 256 Kbit Flash boot memory. It is divided into four equal-sized
    blocks that can be accessed with user-specified addresses. This secondary memory
    brings the ability to execute code and update the main Flash concurrently.
❏ 64 Kbit SRAM. The SRAM's contents can be protected from a power failure by
    connecting an external battery.
❏ CPLD with 16 Output Micro⇔Cells (OMCs) and 24 Input Micro⇔Cells (IMCs). The
    CPLD may be used to efficiently implement a variety of logic functions for internal
    and external control. Examples include state machines, loadable shift registers, and
    loadable counters. The CPLD can also generate eight external chip selects.
❏ Decode PLD (DPLD) that decodes address for selection of internal memory blocks.
❏ 52 individually configurable I/O port pins that can be used for the following functions:
    • MCU I/Os
    • PLD I/Os
    • Latched MCU address output
    • Special function I/Os.
    • I/O ports may be configured as open-drain outputs.
❏ Standby current as low as 50 A for 5 V devices.
❏ Built-in JTAG compliant serial port allows full-chip In-System Programmability (ISP).
    With it, you can program a blank device or reprogram a device in the factory or the field.
❏ Internal page register that can be used to expand the microcontroller address space by a factor of 256.
❏ Internal programmable Power Management Unit (PMU) that supports a low power mode
    called Power Down Mode. The PMU can automatically detect a lack of microcontroller activity
   and put the PSD4000 into Power Down Mode.
❏ Erase/Write cycles:
    • Flash memory 100,000 minimum
    • PLD 1,000 minimum
    • 15 year data retention

Application

• A secondary Flash memory for boot or data
• Over 3,000 gates of Flash programmable logic
• 64 Kbit SRAM
• Reconfigurable I/O ports
• Programmable power management.

Specifications

Symbol	Parameter	Condition	Min	Max	Unit
T_STG	Storage Temperature	PLDCC	65	+ 125	°C
	Operating Temperature	CERDIP	0	+70	°C
	Operating Temperature	PLASTIC	40	+85	°C
	Voltage on any Pin	With Respect to GND	-0.6	+ 7	V
V_PP	Programming Supply Voltage	With Respect to GND	-0.6	+14	V
V_CC	Supply Voltage	With Respect to GND	0.6	+7	V
	ESD Protection			>2000	V

PSD4000

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