Features: · Digitally programmable in 256 steps· Monotonic pulse-width-vs-address variation· Rising edge triggered· Two separate outputs: inverting & non-inverting· Precise and stable pulse width· Input & outputs fully TTL interfaced & buffered· 10 T2L fan-out capability· Fits standard...
PPG38F: Features: · Digitally programmable in 256 steps· Monotonic pulse-width-vs-address variation· Rising edge triggered· Two separate outputs: inverting & non-inverting· Precise and stable pulse widt...
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The timing definitions and restrictions for the PPG38F are shown in Figure 1. The unit is activated by a rising edge on the TRIG input. After a time, TTO (called the inherent delay), the rising edge of the pulse appears at OUT. The duration of the pulse is given by the above equation. For the duration of the pulse, the device ignores subsequent triggers. Once the falling edge of the pulse has appeared at OUT, an additional time, TOTR, is required before the device can respond to the next trigger.
At power-up, the state of the PPG38F is unknown. Consequently, after power is applied, the unit may not respond to input triggers for a time equal to the maximum pulse width, PWT. After this time, the unit will function properly. If your application requires that the device function immediately, issue a quick reset at power-up.
PARAMETER | SYMBOL | MIN | MAX | UNITS | NOTES |
DC Supply Voltage | VCC | -0.3 | 7.0 | V | |
Input Pin Voltage | VIN | -0.3 | VDD+0.3 | V | |
Storage Temperature | TSTRG | -55 | 150 | C | |
Lead Temperature | TLEAD | 300 | C | 10 sec |
The PPG38F-series device is a 8-bit digitally programmable pulse generator. The width, PWA, depends on the address code (A7-A0) according to the following formula:
PWA = PW0 + TINC * A
where A is the address code, TINC is the incremental pulse width of the device, and PW0 is the inherent pulse width of the device. The incremental width is specified by the dash number of the device and can range from 0.5ns through 400ns, inclusively. RESET is held LOW during normal operation. When it is brought HIGH, OUT and OUT/ are forced into LOW and HIGH states, respectively, and the unit is ready for the next trigger input. The address is not latched and must remain asserted while the output pulse is active.