PM6341

· Integrates a full-featured E1 transceiver in a single device with analog circuitry for receiving and transmitting G.703 2048 kbit/s compatible signals and digital circuitry for terminating the duplex digital signal.
· Pin compatible with the PMC PM4341A T1 Framer/Transceiver device.
· Provides an 8-bit microprocessor bus interface for configuration, control, and status monitoring.
· Low power CMOS technology.
· Available in either a 68 pin PLCC or an 80 pin PQFP package.
The receiver section:
· Provides analog circuitry for receiving a G.703 2048 kbit/s signal with up to 6 dB of cable attenuation. Direct digital inputs are also provided to allow for bypassing the analog front-end.
· Recovers clock and data using a digital phase locked loop for high jitter tolerance. A direct clock input is provided to allow clock recovery to be bypassed.
· Accepts dual rail or single rail digital PCM inputs.
· Supports HDB3 or AMI line code.
· Accepts gapped data streams to support higher rate demultiplexing.
· Frames to a G.704 2048 kbit/s signal within 1 ms.
· Frames to the signalling multiframe alignment when enabled.
· Frames to the CRC multiframe alignment when enabled.
· Provides loss of signal detection, and indicates loss of frame alignment (OOF), loss of signalling multiframe alignment and loss of CRC multiframe alignment.
· Supports line and path performance monitoring according to ITU-T recommendations.
Accumulators are provided for counting:
· CRC-4 errors to 1000 per second;
· Far end block errors to 1000 per second;
· Frame sync errors to 127 per second; and
· Line code violations to 8191 per second.
· Indicates the reception of remote alarm and remote multiframe alarm.
· Indicates the reception of alarm indication signal (AIS) and time slot 16 AIS.
· Declares RED and AIS alarms using Q.516 recommended integration periods.
· Provides an HDLC/LAPD interface for terminating a data link. Supports polled, interrupt-driven, or DMA servicing of the HDLC interface.
· Optionally extracts the data link from timeslot 16 (64 kbit/s), which may be used to receive common channel signalling, or from any combination of the national bits in timeslot 0 of non-frame alignment signal frames (4 kbit/s - 20 kbit/s).
· Provides a two-frame elastic store buffer for jitter and wander attenuation that performs controlled slips and indicates slip occurrence and direction.
· Provides channel associated signalling extraction, with optional data inversion, programmable idle code substitution, and up to 3 multiframes of signalling debounce on a per-timeslot basis.
· Provides trunk conditioning which forces programmable trouble code substitution and signalling conditioning on all timeslots or on selected timeslots.
· Optionally provides dual rail digital PCM output signals to allow BPV transparency. Also supports unframed mode.
· Supports transfer of received PCM and signalling data to 2048 kbit/s backplane buses.
The transmitter section:
· Supports transfer of transmitted PCM and signalling data from 2048 kbit/s backplane buses.
· Formats data to create a G.704 2048 kbit/s signal. Optionally inserts signalling multiframe alignment signal. Optionally inserts CRC multiframe structure including optional transmission of far end block errors.
· Optionally accepts dual rail digital PCM inputs to allow BPV transparency. Also supports unframed mode.
· Provides channel associated signalling insertion, programmable idle code ubstitution, digital milliwatt code substitution, and data inversion on a per timeslot basis.
· Provides trunk conditioning which forces programmable trouble code substitution and signalling conditioning on all timeslots or on selected timeslots.
· Supports transmission of the alarm indication signal (AIS), timeslot 16 AIS, remote alarm signal or remote multiframe alarm signal.
· Provides an HDLC/LAPD interface for generating a data link. Supports polled, interrupt-driven, or DMA servicing of the HDLC interface.
· Optionally inserts the data link into timeslot 16 (64 kbit/s), which may be used to transmit common channel signalling, or into any combination of the national bits in timeslot 0 of non-frame alignment signal frames (4 kbit/s - 20 kbit/s).
· Provides a digital phase locked loop for generation of a low jitter transmit clock.
· Provides a FIFO buffer for jitter attenuation and rate conversion in the transmitter. FIFO full or empty indication allows for bit-stuffing in higher rate multiplexing applications.
· Supports HDB3 or AMI line code.
· Provides analog circuitry for transmitting a G.703 compatible 2048 kbit/s signal on a 75 W coaxial line or a 120 W symmetrical line. Digitally programmable line build out is provided.
· Provides dual rail or single rail digital PCM output signals.

The PM6341 E1 Framer/Transceiver (E1XC) is a feature-rich device suitable for muse in many E1 systems PM6341 (such as CSU, DSU, CH BANK, MUX, DPBX, DACS,  and ESDX) PM6341 with a minimum of external circuitry. The E1XC is software configurable, allowing feature selection without changes to external wiring. On the receive side, the E1XC recovers clock and data and can be configured to frame to a basic G.704 2048 kbit/s signal or also frame to the signalling multiframe alignment signal and the CRC multiframe alignment signal.

Analog circuitry of PM6341  is provided to allow direct reception of a G.703 2048 kbit/s signal with up to 6 dB of loss by using only an external transformer and passive components.

The E1XC PM6341 also supports detection of various alarm conditions such as loss of signal, loss of frame, loss of signalling multiframe, loss of CRC multiframe, and reception of remote alarm signal, remote multiframe alarm signal, alarm indication signal, and timeslot 16 alarm indication signal. The E1XC detects and indicates the presence of remote alarm ofPM6341 and AIS patterns and also integrates red and AIS alarms as per industry specifications.

Performance monitoring of PM6341 with accumulation of CRC-4 errors, far end block errors, framing bit errors, and line code violation is provided. The E1XC also detects and terminates HDLC messages on a data link. The data link may be extracted from timeslot 16 and used for common channel signalling or may be extracted from the national bits.

An elastic store of PM6341 for slip buffering and adaptation to backplane timing is provided, as is a channel associated signalling extractor that supports signalling debounce, signalling freezing, idle code substitution, and data inversion on a per-timeslot basis. Receive side data and signalling trunk conditioning is also provided. On the transmit side, the E1XC generates framing for a basic G.704 2048 kbit/s signal, or framing can be optionally disabled. The signalling multiframe alignment signal of PM6341 may be optionally inserted and the CRC multiframe structure may be optionally inserted.

Internal analog circuitry of PM6341 allows direct transmission of a G.703 2048 kbit/s signal into either a 75 W or 120 W line using only an external transformer.

Channel associated signalling insertion, idle code substitution, digital milliwatt tone substitution, and data inversion of PM6341 on a per-timeslot basis is also supported. Transmit side data and signalling trunk conditioning is provided.

HDLC messages on a data link can be transmitted. The data link may be inserted into timeslot 16 and used for common channel signalling or may be inserted into the national bits. The E1XC can generate a low jitter transmit clock and provides a FIFO for transmit jitter attenuation. When not used for jitter attenuation, the full or empty status of this FIFO is made available to facilitate higher order multiplexing applications by controlling bit-stuffing logic.

Interfaces of PM6341 include both a parallel microprocessor port for controlling the operation of the device and a serial PCM interface that allows 2048 kbit/s backplanes to be directly supported. Tolerance of gapped clocks allows other backplane rates to be supported with a minimum of external logic.