Features: • C compiler optimized architecture:- Optional extended instruction set designed to optimize re-entrant code• 100,000 erase/write cycle Enhanced Flash program memory typical• 1,000,000 erase/write cycle Data EEPROM memory typical• Flash/Data EEPROM Retention: 100 ...
PIC18F8722: Features: • C compiler optimized architecture:- Optional extended instruction set designed to optimize re-entrant code• 100,000 erase/write cycle Enhanced Flash program memory typical...
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SpecificationsDescriptionThe PIC1018SCL is one member of the PIC1018 family which is designed as o...
• C compiler optimized architecture:
- Optional extended instruction set designed to optimize re-entrant code
• 100,000 erase/write cycle Enhanced Flash program memory typical
• 1,000,000 erase/write cycle Data EEPROM memory typical
• Flash/Data EEPROM Retention: 100 years typical
• Self-programmable under software control
• Priority levels for interrupts
• 8 x 8 Single-Cycle Hardware Multiplier
• Extended Watchdog Timer (WDT):
- Programmable period from 4 ms to 131s
• Single-Supply In-Circuit Serial Programming™ (ICSP™) via two pins
• In-Circuit Debug (ICD) via two pins
• Wide operating voltage range: 2.0V to 5.5V
• Fail-Safe Clock Monitor
• Two-Speed Oscillator Start-up
• nanoWatt Technology
Parameter Name | Value |
Program Memory Type | Flash |
Program Memory (KB) | 128 |
CPU Speed (MIPS) | 10 |
RAM Bytes | 3,936 |
Data EEPROM (bytes) | 1024 |
Digital Communication Peripherals | 2-A/E/USART, 2-MSSP(SPI/I2C) |
Capture/Compare/PWM Peripherals | 2 CCP, 3 ECCP |
Timers | 2 x 8-bit, 3 x 16-bit |
ADC | 16 ch, 10-bit |
Comparators | 2 |
Temperature Range (C) | -40 to 125 |
Operating Voltage Range (V) | 2 to 5.5 |
Pin Count | 80 |
Ambient temperature under bias.......................................................-40°C to +125°C
Storage temperature ........................................................................... -65°C to +150°
Voltage on any pin with respect to VSS (except VDD and MCLR)..-0.3V to (VDD + 0.3V)
Voltage on VDD with respect to VSS ...................................................... -0.3V to +7.5V
Voltage onMCLR with respect to VSS (Note 2) ..................................... 0V to +13.25V
Total power dissipation (Note 1) ..........................................................................1.0W
Maximum current out of VSS pin .......................................................................300 mA
Maximum current into VDD pin ..........................................................................250 mA
Input clamp current, IIK (VI < 0 or VI > VDD)................................................... ±20 mA
Output clamp current, IOK (VO < 0 or VO > VDD) ............................................ ±20 mA
Maximum output current sunk by any I/O pin......................................................25 mA
Maximum output current sourced by any I/O pin .................................................25 mA
Maximum current sunk by all ports ....................................................................200 mA
Maximum current sourced by all ports ................................................................200 mA
Note 1: Power dissipation is calculated as follows:
Pdis = VDD x {IDD IOH} + {(VDD VOH) x IOH} + (VOL x IOL)
2: Voltage spikes below VSS at the RG5/MCLR/VPP pin, inducing currents greater than 80 mA, may cause latch-up. Thus, a series resistor of 50-100 should be used when applying a "low" level to the RG5/MCLR/ VPP pin, rather than pulling this pin directly to VSS.
† NOTICE: Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at those or any other conditions above those
indicated in the operation listings of this specification is not implied. Exposure to maximum rating conditions for
extended periods may affect device reliability.