Features: C compiler optimized architecture with optiona extended instruction set
100,000 erase/write cycle Enhanced Flash program memory typical
1,000,000 erase/write cycle Data EEPROM memory typical
Flash/Data EEPROM Retention: > 40 years
Self-programmable under software control
Priority levels for interrupts
8 x 8 Single Cycle Hardware Multiplier
Extended Watchdog Timer (WDT):
- Programmable period from 41 ms to 131s
Single-Supply 5V In-Circuit Serial Programming(TM) (ICSP(TM)) via two pins
In-Circuit Debug (ICD) via two pins
Wide operating voltage range: 2.0V to 5.5V
Message bit rates up to 1 Mbps
Conforms to CAN 2.0B ACTIVE Specification
Fully backward compatible with PIC18XXX8 CAN modules
Three modes of operation:
- Legacy, Enhanced Legacy, FIFO
Three dedicated transmit buffers with prioritization
Two dedicated receive buffers
Six programmable receive/transmit buffers
Three full 29-bit acceptance masks
16 full 29-bit acceptance filters w/ dynamic association
DeviceNet(TM) data byte filter support
Automatic remote frame handling
Advanced error management features
Application
In many applications, the ability to detect a drop below,or rise above a particular threshold is desirable. For example, the HLVD module could be periodically enabled to detect Universal Serial Bus (USB) attach or detach. This assumes the device is powered by a lower voltage source than the USB when detached. An attach would indicate a high-voltage detect from, for example,3.3V to 5V (the voltage on USB) and vice versa for a detach. This feature could save a design a few extra components and an attach signal (input pin).
For general battery applications, Figure 22-4 shows a possible voltage curve. Over time, the device voltage decreases. When the device voltage reaches voltage VA, the HLVD logic generates an interrupt at time TA.The interrupt could cause the execution of an ISR,which would allow the application to perform "house-keeping tasks" and perform a controlled shutdown before the device voltage exits the valid operating range at TB. The HLVD, thus, would give the applica-tion a time window, represented by the difference between TA and TB, to safely exit.
Specifications
| Program Memory Type |
Flash |
| Program Memory (KB) |
32 |
| CPU Speed (MIPS) |
10 |
| RAM Bytes |
1,536 |
| Data EEPROM (bytes) |
256 |
| Digital Communication Peripherals |
1-A/E/USART, 1-MSSP(SPI/I2C) |
| Capture/Compare/PWM Peripherals |
1 CCP, 1 ECCP |
| Timers |
1 x 8-bit, 3 x 16-bit |
| ADC |
11 ch, 10-bit |
| Comparators |
2 |
| CAN |
1 ECAN |
| Temperature Range (C) |
-40 to 125 |
| Operating Voltage Range (V) |
2 to 5.5 |
| Pin Count |
40 |
DescriptionThe contents of register 'f'PIC18F4580 are decremented. If 'd' is '0', the result is placed in W. If 'd' is '1', the result is placed back in register 'f' (default)
If the result is '0', the next instruction which is already fetched is discarded and a NOP is executed instead, making it a two-cycle instruction.
If 'a' is '0', the Access Bank is selected.
If 'a' is '1', the BSR is used to select the GPR bank (default).
If 'a' is '0' and the extended instruction set is enabled, this instruction operates in Indexed Literal Offset Addressing mode whenever f 95 (5Fh). See
Section 25.2.3 "Byte-Oriented and
Bit-Oriented Instructions in Indexed
Literal Offset Mode" for details.
PIC18F4580 Data Sheet
