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PIC18F1330

Features: • C compiler optimized architecture with optional extended instruction set• Flash memory retention: > 40 years• Self-programmable under software control• Priority levels for interrupts• 8 x 8 Single-Cycle Hardware Multiplier• Extended Watchdog Timer...

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SeekIC No. : 004462122 Detail

PIC18F1330: Features: • C compiler optimized architecture with optional extended instruction set• Flash memory retention: > 40 years• Self-programmable under software control• Priorit...

PIC18F1330 Data Sheet

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Part Number:
PIC18F1330
Supply Ability:
5000

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  • Qty
  • 1~5000
  • Unit Price
  • Negotiable
  • Processing time
  • 15 Days
Total Cost: $ 0.00

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Upload time: 2024/11/25

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Product Details

Description



Features:

• C compiler optimized architecture with optional extended instruction set
• Flash memory retention: > 40 years
• Self-programmable under software control
• Priority levels for interrupts
• 8 x 8 Single-Cycle Hardware Multiplier
• Extended Watchdog Timer (WDT):
- Programmable period from 4 ms to 131s
• Programmable Code Protection
• Single-Supply In-Circuit Serial Programming™ (ICSP™) via two pins
• In-Circuit Debug (ICD) via two pins
• Wide operating voltage range (2.0V to 5.5V)




Pinout

Connection Diagram




Specifications

Parameter Name Value
Program Memory Type Flash
Program Memory (KB) 8
CPU Speed (MIPS) 10
RAM Bytes 256
Data EEPROM (bytes) 128
Digital Communication Peripherals 1-A/E/USART,
Timers 2 x 16-bit
ADC 4 ch, 10-bit
Comparators 3
Temperature Range (C) -40 to 125
Operating Voltage Range (V) 2 to 5.5
Pin Count 18


Ambient temperature under bias......................................................-40°C to +125°C
Storage temperature ...................................................................... -65°C to +150°C
Voltage on any pin with respect to VSS (except VDD and MCLR)..-0.3V to (VDD + 0.3V)
Voltage on VDD with respect to VSS ....................................................... -0.3V to +7.5V
Voltage onMCLR with respect to VSS (Note 2) ........................................ 0V to +13.25V
Total power dissipation (Note 1) .............................................................................1.0W
Maximum current out of VSS pin ...........................................................................300 mA
Maximum current into VDD pin ...............................................................................250 mA
Input clamp current, IIK (VI < 0 or VI > VDD)........................................................ ±20 mA
Output clamp current, IOK (VO < 0 or VO > VDD) ................................................. ±20 mA
Maximum output current sunk by any I/O pin............................................................25 mA
Maximum output current sourced by any I/O pin .......................................................25 mA
Maximum current sunk by all ports ...........................................................................200 mA
Maximum current sourced by all ports ......................................................................200 mA

Note 1: Power dissipation is calculated as follows:
Pdis = VDD x {IDD IOH} + {(VDD VOH) x IOH} + (VOL x IOL)
2: Voltage spikes below VSS at the MCLR/VPP/RA5/FLTA pin, inducing currents greater than 80 mA, may cause latch-up. Thus, a series resistor of 50-100 should be used when applying a "low" level to the MCLR/ VPP/RA5/FLTA pin, rather than pulling this pin directly to VSS.

† NOTICE: Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to the
device. This is a stress rating only and functional operation of the device at those or any other conditions above those
indicated in the operation listings of this specification is not implied. Exposure to maximum rating conditions for
extended periods may affect device reliability.




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