Features: • Sixteen line receivers meet or exceed the requirements of theANSI TIA/EIA-644-1995 Standard
• Designed for signaling rates up to 660 Mbps
• 0V to 3V common-mode input voltage range
• Operates from a single 3.3V supply
• Typical propagation delay time: 2.6ns
• Output skew 100ps (typical)
• Part-to-part skew is less than 1ns
• Integrated 110-Ohm termination on PI90LVT386
• Low Voltage TTL (LVTTL) levels are 5V tolerant
• Open-circuit fail safe
• Flow-through pin out
• Packaging (Pb-free & Green available):- 64-Pin Thin Shrink Small Output TSSOP (A)Pinout
SpecificationsSupply Voltage Range, VDD(1) ....................................... 0.5V to 4V
Voltage Range: ............................................... Enables or ROUT
0.5V to VDD +2V
RIN+ or RIN ........................................................................ 0.5V to 4V
Electrostatic Discharge(2):
RIN+, RIN, and GND ....................... Class 3, A: 10kV, B:700V
All Pins .............................................. Class 3, A: 8kV, B:600V
Storage Temperature Range ............................. 65°C to 150°C
Lead Temperature 1, 6mm (1/16 inch)
from case for 10 seconds .................................................... 260°C
† Stresses beyond those listed under "Absolute Maximum Ratings" maycause permanent damage to the device. These are stress ratings only, andfunctional operation of the device at these or any other conditions beyondthose indicated under "Recommended Operating Conditions" is notimplied. Exposure to Absolute-Maximum-Rated conditions for extendedperiods may affect device reliability.
Notes:
1. All voltage values, except differential I/O bus voltages, are withrespect to ground terminal.
2. Tested in accordance with MIL-STD-883C Method 3015.7
DescriptionThe PI90LVx386 family consists of sixteen differential line receiverswith 3-state outputs that implement Low-Voltage DifferentialSignaling (LVDS). Any of the differential receivers will provide avalid logical output state with a ±100mV differential input voltagewithin the input common-mode voltage range that allows 0 to 3V ofground potential difference between two LVDS nodes. The independentEN pins of PI90LVx386 family can be used to place the outputs in either a normal logicstate (high or low logic levels) or a high-impedance state. In highimpedancestate, outputs neither load nor drive the bus lines.
The intended application of PI90LVx386 family, and their signalingtechniques, is for point-to-point baseband data transmission overcontrolled impedance media of approximately 100-ohms with a100-Ohm termination resistor. The PI90LVT386 integrates the terminatingresistors while the PI90LV386 requires external resistors.
The transmission media may be printed circuit board traces,backplanes, or cables. The PI90LV386's 16 receivers integrated intothe same substrate allow precise timing alignment.
PI90LVx386 family are characterized for operation from 40°C to 85°C.
PI90LV386 Data Sheet
