PI90LV14

The PI90LV14 implements low voltage differential signaling (LVDS)to achieve clocking rates as high as 320MHz with low skew.

The PI90LV14 is a low-skew 1:5 clock distribution chip whichincorporates multiplexed clock inputs to allow for distribution of alower-speed, single-ended clock or a high-speed system clock.When LOWthe SEL pin will select the differential clock input.

The common PI90LV14 enable (EN) is synchronous so that the outputs willonly be enabled/disabled when they are already in the LOW state.

PI90LV14 avoids any chance of generating a runt clock pulse when thedevice is enabled/disabled as can happen with an asynchronouscontrol. Because the internal flip-flop of PI90LV14 is clocked on the falling edgeof the input clock, all associated specification limits are referencedto the negative edge of the clock input.

The intended application of PI90LV14 and signaling techniqueis for high-speed clock distribution between boards.