PI74FCT162511T

Storage Temperature .................................................................... 65°C to +150°C
Ambient Temperature with Power Applied .................................... 40°C to +85°C
Supply Voltage to Ground Potential (Inputs & Vcc Only) .............. 0.5V to +7.0V
Supply Voltage to Ground Potential (Outputs & D/O Only) ........... 0.5V to +7.0V
DC Input Voltage ............................................................................ 0.5V to +7.0V
DC Output Current ..................................................................................... 120 mA
Power Dissipation ..........................................................................................1.0W

Note:
Stresses greater than those listed under MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.

Pericom Semiconductor's PI74FCT series of logic circuits are produced in the Company's advanced 0.8 micron CMOS technology, achieving industry leading speed grades.

The PI74FCT16511T and PI74FCT162511T are high-speed, lowpower 16-bit registered/latched transceiver with parity which combines D-type latches and D-type flip-flops to allow data flow in transparent, latched or clocked modes. PI74FCT16511T and PI74FCT162511T have a parity generator/ checker in the A-to-B direction and a parity checker in the B-to-A direction. Error checking is done at the byte level with separate parity bits for each byte. One error flag for each direction (A-to-B or B-to-A) exists to indicate an error for either byte in either direction. The parity error flags which are open drain outputs, PI74FCT16511T and PI74FCT162511T can be tied together and/or tied with flags from other devices to form a single error flag or interrupt. To disable the error flag during combinational transitions, a designer can disable the parity error flag by the OExx control pins.

The operation in A-to-B direction is controlled by LEAB, CLKAB and OEAB control pins, and the operation in B-to-A direction is controlled by LEBA, CLKBA and OEBA control pins. GEN/CHK is used to select the operation of A-to-B direction, while B-to-A direction is always in checking mode. The ODD/EVEN select is common between the two directions. Independent operation of PI74FCT16511T and PI74FCT162511T can be achieved between the two directions by using the corresponding control lines except for the ODD/EVEN control.