PI74AVC+16345

Supply voltage range, VCC .................................................... –0.5V to +4.6V
Input voltage range, VI ............................................................ –0.5V to +4.6V
Voltage range applied to any output in the
high-impedance or power-off state, VO
(1) .................... –0.5V to +4.6V
Voltage range applied to any output in the
high or low state, VO
(1,2) ............................................... –0.5V to VCC +0.5V
Input clamp current, IIK (VI <0) ............................................. –50mA
Output clamp current, IOK (VO <0) ....................................... –50mA
Continuous output current, IO ............................................................. ±50mA
Continuous current through each VCC or GND .................. ±100mA
Package thermal impedance, qJA(3): package A .................... 64°C/W
package K .................... 48°C/W
Storage Temperature range, Tstg .......................................–65°C to 150°C

Note: Stresses greater than those listed under MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.

Pericom Semiconductor's PI74AVC+ series of logic circuits of PI74AVC+16345 are produced using the Company's advanced submicron CMOS technology, achieving industry leading speed.

The PI74AVC+16345 is ideal for driving memory modules in systems where multiple memory modules are used. One each of the four output banks drive a different module; modules can be added or removed without affecting the signal integrity of the other modules in the system. Dual clock enables (CEx) allow use of the device in high-speed memory interleaving applications where the clock of PI74AVC+16345 can be alternately enabled and disabled, allowing the address to be held for additional cycles during memory access.

To ensure the high-impedance state during power up or power down, OE should be tied to VCC through a pullup resistor; the minimum value of the resistor is determined by the current sinking capability of the driver.