PI6CU877

Features:

• PLL clock distribution optimized for DDR2 SDRAM applications.
• Distributes one differential clock input pair to ten differential clock output pairs.
• Differential Inputs (CLK, CLK) and (FBIN, FBINFBIN)
• Input OE/OS: LVCMOS
• Differential Outputs (Y[0:9], Y[0:9] and (FBOUT, FBOUT)
• External feedback pins (FBIN, FBIN) are used tosynchronize the outputs to the clock input.
• Operates at AVDD = 1.8V for core circuit and internal PLL, and VDDQ = 1.8V for differential output drivers
• Packaging (Pb-free & Green available): 52-ball VFBGA (NF)




Specifications

Product Specs: Voltage: 1.8V Function: Zero-Delay Buffer Jitter: 40ps Skew: 40ps Speed: 270MHz I/O: SSTL18 Temp: Com Outputs: 10 Pins: 52 Packages: VFBGA (NF52) Pb-Free and Green: Yes - more info RoHS Material Declarations: PI6CU877NFE MDR (pdf)PI6CUA877NFE MDR (pdf)

Symbol	Parameter	Min.	Max.	Units
VCC,AVDD	I/O supply voltage range and analog /core supply voltage range	-0.5	2.5	V
VI	Input voltage range	-0.5	VDDQ +0.5
VO	Output voltage range	-0.5
IIK	Input Clamp Current	-50	50	mA
IOK	Output clamp current	-50	±50
IO	Continuous output current	-50	±100
IO(PWR)	Continuous current through each VDDQ or GND	-100	0.85
TSTG	Storage temperature	-65	150

Note:
1. Stress beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device.

Description

1.8V, 270 MHz, 10 Output SSTL-18 Clock Driver for DDR2 DIMM

PI6CU877 PLL clock driver is developed for Registered DDR2 DIMM applications with 1.8V operation and differential data input and output levels.

The device is a zero delay buffer that distributes a differential clock input pair (CLK, CLK) to eleven differential pairs of clock outputs which includes feedback clock (Y[0:9], Y[0:9]; FBOUT, FBOUT).

The clock outputs are controlled by CLK/CLK, FBOUT, FBOUT, the LVCMOS (OE, OS) and the Analog Power input (AVDD). When OE is LOW the outputs except FBOUT, FBOUT, are disabled while the internal PLL continues to maintain its locked-in frequency. OS is a program pin that must be tied to GND or VDD. When OS is high, OE will function as described above. When OS is LOW, OE has no effect on Y7/Y7, PI6CU877 is free running. When AVDD is grounded, the PLL is turned off and bypassed for test purposes.

When CLK/CLK are logic low, the PI6CU877 will enter a low power mode. An input logic detection circuit will detect the logic low level and perform a low power state where all Y[0:9], Y[0:9]; FBOUT, FBOUT, and PLL are OFF.

PI6CU877 is a high performance, low skew, and low jitter PLL clock driver, and it is also able to track Spread Spectrum Clocking (SSC) for reduced EMI.