PI6C3991

Features:

· All output pair skew <100ps typical (250 Max.)
· 3.75 MHz to 80 MHz output operation
· User-selectable output functions
· Selectable skew to 18ns
· Inverted and Non-Inverted
· Operation at ½ and ¼ input frequency
· Operation at 2X and 4X input frequency (input as low as 3.75 MHz, x4 operation)
· Zero input-to-output delay
· 50% duty-cycle outputs
·• LVTTL outputs drive 50-ohm terminated lines
· Operates from a single 3.3V supply
· Low operating current
· Available in 32-pin PLCC (J) package
· Jitter < 200ps peak-to-peak (< 25ps RMS)


Pinout




Specifications

Storage Temperature ...................................... –65°C to +150°C
Ambient Temperature with
Power Applied .................................................–55°C to +125°C
Supply Voltage to Ground Potential .................. –0.5V to +7.0V
DC Input Voltage ............................................... –0.5V to +7.0V
Output Current into Outputs (LOW) ............................... 64mA
Static Discharge Voltage ............................................... >2001V
(per MIL-STD-883, Method 3015)
Latch-Up Current .........................................................>200mA


Description

PI6C3991 offers selectable control over system clock functions.These multiple-output clock drivers provide the system integrator with functions necessary to optimize the timing of high-performance computer systems. Eight individual drivers, arranged as four pairs of user-controllable outputs, PI6C3991 can each drive terminated transmission lines with impedances as low as 50 ohms while delivering minimal and specified output skews and full-swing logic levels (LVTTL).

Each output of PI6C3991 can be hardwired to one of nine skews or function configurations. Delay increments of 0.7ns to 1.5ns are determined by the operating frequency with outputs able to skew up to ±6 time units from their nominal "zero" skew position. The completely PI6C3991 integrated PLL allows external load and transmission line delay effects to be canceled. The user can create output-to-output skew up to ±12 time units.

Divide-by-two and divide-by-four output functions of PI6C3991 are provided for additional flexibility in designing complex clock systems. When combined with the internal PLL, these divide functions allow distribution of a low-frequency clock that can be multiplied by two or four at the clock destination. PI6C3991 feature allows flexibility and simplifies system timing distribution design for complex high-speed systems.