PI6C2972

targeted for high-performance CISC or RISC processor based systems. With output frequencies of up to 125 MHz and skews of 550ps the PI6C2972 are ideally suited for most synchronous systems. The PI6C2972 offers twelve low skew outputs plus a feedback and sync output for added flexibility and ease of system implementation.

The PI6C2972 features an extensive level of frequency programmability between the 12 outputs as well as the input vs output relationships. Using the select lines output frequency ratios of 1:1, 2:1, 3:1, 3:2, 4:1, 4:3, 5:1, 5:2, 5:3, 6:1 and 6:5 between outputs can be realized by pulsing low one clock edge prior to the coincident edges of the Qa and Qc outputs. The Sync output will indicate when the coincident rising edges of the above relationships will occur. The PowerOn Reset ensures proper programming if the frequency select pins are set at power up. If the fselFB2 pin is held high, it may be necessary to apply a reset after powerup to ensure synchronization between the QFB output and the other outputs.

The internal poweron reset is designed to provide this function, but with powerup conditions being dependent, PI6C2972 is difficult to guarantee.  All other conditions of the fsel pins will automatically synchronize during PLL lock acquisition.

The PI6C2972 offers a very flexible output enable/disable scheme. Note that all of the control inputs on it have internal pull up resistors.

The PI6C2972 is fully 3.3V compatible and requires no external loop filter components. All inputs accept LVCMOS/LVTTL compatible levels while the outputs provide LVCMOS levels with the capability to drive 50-ohm transmission lines. For series terminated lines each PI6C2972 output can drive two 50-ohm lines in parallel thus effectively doubling the fanout of the device.