PI6C2516

· High Performance Phase-Locked Loop Clock Distribution for Synchronous DRAM, server and networking applications.
· Zero Input-to-Output delay: Distribute One Clock Input to four banks of four outputs, with separate output enables for each bank.
· Allow Clock Input to have Spread Spectrum modulation for EMI reduction. The clock outputs track the Clock Input modulation.
· Maximum clock frequency of 150 MHz.
· Low jitter: Cycle-to-Cycle jitter ±100ps max
· Operates at 3.3V VCC
· Available Packaging: - 48-pin TSSOP (Thin Shrink Small Outline) (A)

The PI6C2516 family is a low-skew, low jitter, phase-locked loop (PLL) clock driver, distributing high-frequency clock signals for SDRAM, server and networking applications. By connecting the feedback FB_OUT output to the feedback FB_IN input, the propagation delay from the CLK input to any clock output will be nearly zero. This zero-delay feature of PI6C2516 allows the CLK input clock to be distributed, providing 4 banks of four outputs.

For test purposes, the PLL can be bypassed by strapping the AVCC to ground.

The PI6C2516 family has the same pinout as the TI CDC2516, with the added feature of allowing Spread Spectrum clock input.