PI6C2510-133

• Operating Frequency up to 150 MHz
• Low-Noise Phase-Locked Loop Clock Distribution that meets 133 MHz Registered DIMM Synchronous DRAM modules for server/workstation/PC applications
• Allows Clock Input to have Spread Spectrum modulation for EMI reduction
• Zero Input-to-Output delay: Distribute one Clock Input to one Bank of Ten outputs, with an output enable.
• Low jitter: Cycle-to-Cycle jitter ±75ps max.
• On-chip series damping resistor at clock output drivers for low noise and EMI reduction
• Operates at 3.3V VCC
• Packaging(Pb-free & Green available): - 24-pin TSSOP (L)

The PI6C2510-133 is a "quiet," low-skew, low-jitter, phase-locked loop (PLL) clock driver, distributing high-frequency clock signals for SDRAM and server applications. By connecting the feedback FB_OUT output to the feedback FB_IN input, the propagation delay from the CLK_IN input to any clock output will be nearly zero.

This zero-delay PI6C2510-133 feature allows the CLK_IN input clock to be distributed, providing one clock input to one bank of ten outputs, with an output enable.

PI6C2510-133 clock driver is designed to meet the PC133 SDRAM Registered DIMM specification. For test purposes, the PLL can be bypassed by strapping AVCC to ground.