PI6C2509-133

Features:

· Operating Frequency up to 150 MHz
· Low-Noise Phase-Locked Loop Clock Distribution to meet 133 MHz Registered DIMM Synchronous DRAM module pecifications for server/workstation/PC applications
· Allows Clock Input to have Spread Spectrum modulation for EMI reduction
· Zero Input-to-output delay: Distribute One Clock Input to one bank of five and one bank of four outputs, with separate output enables
· Low jitter: Cycle-to-Cycle jitter ±75ps max.
· On-chip series damping resistor at clock output drivers for low noise and EMI reduction
· Operates at 3.3V VCC
· Package: Plastic 24-pin TSSOP (L)




Pinout






Specifications

Symbol	Parameter	Min.	Max.	Units
VI	Input voltage range	-0.5	VCC + 0.5	V
VO	Output voltage range
VO_DC	DC output current		+0.5
IO_DC	DC output current		100	mA
Power	Maximum power dissipation at TA= 55 in still air		1.0	W
TSTG	Storage temperature	-65	150

Note:
1. Stress beyond those listed under "absolute maximum ratings" may cause permanent damage to the device.

Product Specs: Voltage: 3.3V Function: Zero-Delay Buffer Jitter: 75ps Skew: 150ps Speed: 150MHz I/O: CMOS Temp: Ind Outputs: 9 Pins: 24 Packages: TSSOP (L24) Pb-Free and Green: Yes - more info RoHS Material Declarations: PI6C2509-133LE MDR (pdf)




Description

The PI6C2509-133 is a "quiet," low-skew, low-jitter, phase-locked loop (PLL) clock driver, distributing low-noise clock signals for SDRAM and server applications. By connecting the feedback FB_OUT output to the feedback FB_IN input, the propagation delay from the CLK_IN input to any clock output will be nearly zero. This zero-delay PI6C2509-133 feature allows the CLK_IN input clock to be distributed, providing 5 clocks for the first bank, and an additional 4 clocks for the second bank.

PI6C2509-133 clock driver is designed to meet the PC133 SDRAM Registered DIMM specification. For test purposes, the PLL can be bypassed by strapping AVCC to ground.