PI6C2504

Features:

· High-Performance Phase-Locked-Loop Clock Distribution for Networking
· Registered DIMM Synchronous DRAM modules for server/workstation/PC applications
· Allows Clock Input to have Spread Spectrum modulation for EMI reduction
· Zero Input-to-Output delay
· Low jitter: Cycle-to-Cycle jitter ±100ps max.
· On-chip series damping resistor at clock output drivers for low noise and EMI reduction
· Operates at 3.3V VCC
· Wide range of Clock Frequencies up to 80 MHz
· Package: Plastic 16-pin QSOP Package (Q)

Pinout






Specifications

Symbol	Parameter	Min.	Max.	Units
VI	Input voltage range	-0.5	VCC +0.5	V
VO	Output voltage range
IO_DC	DC output current		100	mA
Power	Maximum power dissipation at TA = 55oC in still air		1.0	W
TSTG	Storage temperature	-65	150

Note: Stress beyond those listed under "absolute maximum ratings" may cause permanent damage to the device.

Product Specs: Voltage: 3.3V Function: Zero-Delay Buffer Jitter: 100ps Skew: 200ps Speed: 80MHz I/O: CMOS Temp: Com Outputs: 4 Pins: 16 Packages: QSOP (Q16) Pb-Free and Green: No - more info RoHS Material Declarations: PI6C2504AQE MDR (pdf)PI6C2504QE MDR (pdf)




Description

The PI6C2504 features a low-skew, low-jitter, phase-locked loop (PLL) clock driver, distributing high-frequency clock signals for SDRAM and server applications. By connecting the feedback FB_OUT output to the feedback FB_IN input, the propagation delay from the CLK_IN PI6C2504 input to any clock output will be nearly zero.