PI6C2308

Providing two banks of four outputs, the PI6C2308 is a 3.3V zerodelay buffer designed to distribute clock signals in applications including PC, workstation, datacom, telecom, and high-performance systems. Each bank of four outputs can be controlled by the select inputs as shown in the Select Input Decoding Table.

The PI6C2308 provides 8 copies of a clock signal that has 200ps phase error compared to a reference clock. The skew between the output clock signals for it is less than 200ps. When there are no rising edges on the REF input, it enters a power down state. In this mode, the PLL is off and all outputs are Hi-Z.

This results in less than 12µA of current draw. The Select Input Decoding Table shows additional examples when the PLL shuts down. The PI6C2308 configuration table shows all available devices.

The base part, PI6C2308-1, provides output clocks in sync with a reference clock. With faster rise and fall times, the PI6C2308-1H is the high drive version of the PI6C2308-1. Depending on which output drives the feedback pin, PI6C2308-2 provides 2X and 1X clock signals on each output bank. The PI6C2308-3 allows the user to obtain 4X and 2X frequencies on the outputs. The PI6C2308-4 provides 2X clock signals on all outputs. PI6C2308 (-1, -2, -3, -4) allows bank B to be Hi-Z when all output clocks are not required.The PI6C2308-6 allows bank B to switch from Reference clock to half of the frequency of Reference clock using the control inputs S1 and S2 if Bank A is connected to feedback FBK. In addition, using the control inputs S1 and S2, the PI6C2308-6 allows bank A to switch from Reference clock to 2X the frequency of Reference clock if Bank B is connected to feedback FBK. For testing purposes, the select inputs connect the input clock directly to outputs.