PI6C20800S

Features:

• Phase jitter fi lter for PCIe application
• Eight Pairs of Differential Clocks
• Low skew < 50ps
• Low Cycle-to-cycle jitter < 50ps
• Output Enable for all outputs
• Outputs Tristate control via SMBus
• Power Management Control
• Programmable PLL Bandwidth
• PLL or Fanout operation
• 3.3V Operation
• Packaging (Pb-Free & Green):
- 48-Pin SSOP (V)
- 48-Pin TSSOP (A)




Pinout






Specifications

Product Specs: Voltage: 3.3V Function: Zero-Delay Buffer Jitter: 50ps Skew: 50ps Speed: 95-105MHz I/O: HCSL Temp: Com Outputs: 8 Pins: 48 Packages: TSSOP (A48)SSOP (V48) Pb-Free and Green: Yes - more info RoHS Material Declarations: Not Available

Symbol	Parameters	Min.	Max.	Units
VDD_A	3.3V Core Supply Voltage	-0.5	4.6	V
VDD	3.3V I/O Supply Voltage	-0.5	4.6
VIH	Input HIGH Voltage		4.6
VIL	Input LOW Voltage	-0.5
Ts	Storage Temperature	-65	150
VESD	ESD Protection	2000		V

Note:
1. Stress beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device.




Description

3.3V, 100MHz PCIe Gen II Differential HCSL Clock Buffer. PI6C20800S is a PCI Express, high-speed, low-noise differential clock buffer designed to be a companion to PI6C410BS PCI Express clock generator for Intel server chipsets. The PI6C20800S distributes the differential SRC clock from PI6C410BS to eight differential pairs of clock outputs either with or without PLL. The input SRC clock can be divided by 2 when SRC_DIV# is LOW. The clock outputs are controlled by input selection of SRC_STOP#, PWRDWN# and SMBus, SCLK and SDA. When input of either SRC_STOP# or PWRDWN# is LOW, the output clocks are Tristated. When PWRDWN# is LOW, the SDA and SCLK inputs must be Tristated.