PD45128841-I

· Fully Synchronous Dynamic RAM, with all signals referenced to a positive clock edge
· Pulsed interface
· Possible to assert random column address in every cycle
· Quad internal banks controlled by BA0(A13) and BA1(A12)
· Byte control (×16) by LDQM and UDQM
· Programmable Wrap sequence (Sequential / Interleave)
· Programmable burst length (1, 2, 4, 8 and full page)
· Programmable /CAS latency (2 and 3)
· Ambient temperature (TA): -40 to + 85°C
· Automatic precharge and controlled precharge
· CBR (Auto) refresh and self refresh
· ×4, ×8, ×16 organization
· Single 3.3 V ± 0.3 V power supply
· LVTTL compatible inputs and outputs
· 4,096 refresh cycles / 64 ms
· Burst termination by Burst stop command and Precharge command

Caution  Exposing the device to stress above those listed in Absolute Maximum Ratings could cause permanent damage. The device is not meant to be operated under conditions outside the limits described  in  the  operational  section  of  this  specification.  Exposure  to  Absolute Maximum Rating conditions for extended periods may affect device reliability.

The PD45128841-I is high-speed 134,217,728-bit synchronous dynamic random-access emories, organized as 8,388,608 × 4 × 4, 4,194,304 × 8 × 4, 2,097,152 × 16 × 4 (word × bit × bank), respectively.
The synchronous DRAMs of PD45128841-I achieved high-speed data transfer using the pipeline architecture.

All inputs and outputs of PD45128841-I are synchronized with the positive edge of the clock.

The synchronous DRAMs of PD45128841-I are compatible with Low Voltage TTL (LVTTL).

The PD45128841-I is packaged in 54-pin TSOP (II).