Features: • PC Card Standard 8.1 compliant
• PCI Bus Power Management Interface Specification 1.1 compliant
• Advanced Configuration and Power Interface (ACPI) Specification 2.0 compliant
• PCI Local Bus Specification Revision 2.3 compliant
• PC 98/99 and PC2001 compliant
• Windows Logo Program 2.0 compliant
• PCI Bus Interface Specification for PCI-to-CardBus Bridges
• 1.5-V core logic and 3.3-V I/O cells with internal voltage regulator to generate 1.5-V core VCC
• Universal PCI interfaces compatible with 3.3-V and 5-V PCI signaling environments
• Supports PC Card or CardBus with hot insertion and removal
• Supports 132-MBps burst transfers to maximize data throughput on both the PCI bus and the CardBus
• Supports serialized IRQ with PCI interrupts
• Programmable multifunction terminals
• Many interrupt modes supported
• Serial ROM interface for loading subsystem ID and subsystem vendor ID
• ExCA-compatible registers are mapped in memory or I/O space
• Intel 82365SL-DF register compatible
• Supports ring indicate, SUSPEND, and PCI CLKRUN protocols and PCI bus Lock (LOCK)
• Provides VGA/palette memory and I/O, and subtractive decoding options, LED activity terminals
• Fully interoperable with FireWire and i.LINK implementations of IEEE Std 1394
• Compliant with Intel Mobile Power Guideline 2000
• Fully compliant with provisions of IEEE Std 1394-1995 for a high-performance serial bus and IEEE Std 1394a-2000
• Fully compliant with 1394 Open Host Controller Interface Specification 1.1
• Full IEEE Std 1394a-2000 support includes: connection debounce, arbitrated short reset, multispeed concatenation, arbitration acceleration, fly-by concatenation, and port disable/suspend/resume
• Power-down features to conserve energy in battery-powered applications include: automatic device power down during suspend, PCI power management for link-layer, and inactive ports powered down, ultralow-power sleep mode
• A IEEE Std 1394a-2000 fully compliant cable port at 100M bits/s, 200M bits/s, and 400M bits/s
• Cable port monitors line conditions for active connection to remote node
• Cable power presence monitoring
• Separate cable bias (TPBIAS) for the port
• Physical write posting of up to three outstanding transactions
• PCI burst transfers and deep FIFOs to tolerate large host latency 1−3
• External cycle timer control for customized synchronization
• Extended resume signaling for compatibility with legacy DV components
• PHY-Link logic performs system initialization and arbitration functions
• PHY-Link encode and decode functions included for data-strobe bit level encoding
• PHY-Link incoming data resynchronized to local clock
• Low-cost 24.576-MHz crystal provides transmit and receive data at 100M bits/s, 200M bits/s, and 400M bits/s
• Node power class information signaling for system power management
• Register bits give software control of contender bit, power class bits, link active control bit, and IEEE Std 1394a-2000 features
• Isochronous receive dual-buffer mode
• Out-of-order pipelining for asynchronous transmit requests
• Register access fail interrupt when the PHY SCLK is not active
• PCI power-management D0, D1, D2, and D3 power states
• Initial bandwidth available and initial channels available registers
Application• Card insertion/removal and recognition per the PC Card Standard (release 8.1)
• Speaker and audio applications
• LED socket activity indicators
• PC Card controller programming model
• CardBus socket registersSpecificationsSupply voltage range, VR_PORT . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 1.836 V
VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.3 V to 4 V
VD_PLL15 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 1.836 V
VD_PLL33 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.3 V to 4 V
VCCA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .−0.5 V to 5.5 V
VCCP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .−0.5 V to 5.5 V
Clamping voltage range, VCCP and VCCA . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 6 V
Input voltage range, VI: PCI, CardBus, PHY, miscellaneous . . . .−0.5 V to VCC + 0.5 V
Output voltage range, VO: PCI, CardBus, PHY, miscellaneous . .−0.5 V to VCC + 0.5 V
Input clamp current, IIK (VI < 0 or VI > VCC) (see Note 1) . . . . . . . . . . . . . . . ±20 mA
Output clamp current, IOK (VO < 0 or VO > VCC) (see Note 2) . . . . . . . . . . . . .±20 mA
Operating free-air temperature, TA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .0°C to 70°C
Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . .−65°C to 150°C
Virtual junction temperature, TJ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150°CDescriptionThe PCI4515 controller is a two-function PCI controller compliant with PCI Local Bus Specification, Revision 2.3. Function 0 provides an independent PC Card socket controllers compliant with the PC Card Standard (Release 8.1). The PCI4515 controller provides features that make it the best choice for bridging between the PCI bus and PC Cards, and supports 16-bit, CardBus, or USB custom card interface PC Cards, powered at 5 V or 3.3 V, as required.
All card signals are internally buffered to allow hot insertion and removal without external buffering. The PCI4515 controller is register compatible with the Intel 82365SL-DF ExCA controller. The PCI4515 internal data path logic allows the host to access 8-, 16-, and 32-bit cards using full 32-bit PCI cycles for maximum performance. Independent buffering and a pipeline architecture provide an unsurpassed performance level with sustained bursting. The PCI4515 controller can be programmed to accept posted writes to improve bus utilization.
Function 2 of the PCI4515 controller is compatible with IEEE Std 1394a-2000 and the latest 1394 Open Host Controller Interface Specification. The chip provides the IEEE1394 link and 1-port PHY function and is compatible with data rates of 100, 200, and 400 Mbits per second. Deep FIFOs are provided to buffer 1394 data and accommodate large host bus latencies. The PCI4515 controller provides physical write posting and a highly tuned physical data path for SBP-2 performance.
PCI4515 Data Sheet
