PCI4512ZHK

· PC Card Standard 8.1 Compliant
· PCI Bus Power Management Interface Specification 1.1 Compliant
· Advanced Configuration and Power Interface (ACPI) Specification 2.0 Compliant
· PCI Local Bus Specification Revision 2.3 Compliant
· Windows Logo Program Compliant
· PCI Bus Interface Specification for PCI-to-CardBus Bridges
· Fully Compliant with Provisions of IEEE Std 1394-1995 for a High-Performance Serial Bus and IEEE Std 1394a-2000
· Fully Compliant with 1394 Open Host Controller Interface Specification 1.1
· 1.5-V Core Logic and 3.3-V I/O Cells with Internal Voltage Regulator to Generate 1.5-V Core VCC
· Universal PCI Interfaces Compatible with 3.3-V and 5-V PCI Signaling Environments
· Supports PC Card or CardBus with Hot Insertion and Removal
· Supports 132-MBps Burst Transfers to Maximize Data Throughput on Both the PCI Bus and the CardBus
· Supports Serialized IRQ with PCI Interrupts
· Programmable Multifunction Terminals
· Many Interrupt Modes Supported
· Serial ROM Interface for Loading Subsystem ID and Subsystem Vendor ID
· ExCA-Compatible Registers Are Mapped in Memory or I/O Space
· Intel 82365SL-DF Register Compatible
· Supports Ring Indicate, SUSPEND, and PCI CLKRUN Protocols
· Provides VGA/Palette Memory and I/O, and Subtractive Decoding Options, LED Activity Terminals
· Fully Interoperable with FireWire^TM and i.LINK^TM Implementations of IEEE Std 1394
· Compliant with Intel Mobile Power Guideline 2000
· Full IEEE Std 1394a-2000 Support Includes:Connection Debounce, Arbitrated Short Reset, Multispeed Concatenation,Arbitration Acceleration, Fly-By Concatenation, and Port Disable/Suspend/Resume
· Power-Down Features to Conserve Energy in Battery-Powered Applications Include: Automatic Device Power Down During Suspend, PCI Power Management for Link-Layer, and Inactive Ports Powered Down, Ultralow-Power Sleep Mode
· Two IEEE Std 1394a-2000 Fully Compliant Cable Ports at 100M Bits/s, 200M Bits/s,and 400M Bits/s
· Cable Ports Monitor Line Conditions for Active Connection to Remote Node
· Cable Power Presence Monitoring
· Separate Cable Bias (TPBIAS) for Each Port
· Physical Write Posting of up to Three Outstanding Transactions
· PCI Burst Transfers and Deep FIFOs to Tolerate Large Host Latency
· External Cycle Timer Control for Customized Synchronization
· Extended Resume Signaling for Compatibility with Legacy DV Components