PCI4510R

` PC Card Standard 8.0 Compliant
` PCI Bus Power Management Interface Specification 1.1 Compliant
` Advanced Configuration and Power Interface (ACPI) Specification 2.0 Compliant
` PCI Local Bus Specification Revision 2.2 Compliant
` PC 98/99 and PC2001 Compliant
` PCI Bus Interface Specification for PCI-to-CardBus Bridges
` Fully Compliant with Provisions of IEEE Std 1394-1995 for a High-Performance Serial Bus and IEEE Std 1394a-2000
` Fully Compliant with 1394 Open Host Controller Interface Specification 1.1
` Compatible with Both TPS2211A and TPS2221 PC Card Power Switches
` 1.8-V Core Logic and 3.3-V I/O Cells with Internal Voltage Regulator to Generate 1.8-V Core VCC
` Universal PCI Interfaces Compatible with 3.3-V and 5-V PCI Signaling Environments
` Supports PC Card or CardBus with Hot Insertion and Removal
` Supports 132-MBps Burst Transfers to Maximize Data Throughput on Both the PCI Bus and the CardBus
` Supports Serialized IRQ with PCI Interrupts
` Programmable Multifunction Terminals
` Serial ROM Interface for Loading Subsystem ID and Subsystem Vendor ID
` ExCA-Compatible Registers Are Mapped in Memory or I/O Space
` Intel 82365SLDF Register Compatible
` Supports Ring Indicate, SUSPEND, PCI CCLKRUN Protocol, and PCI Bus Lock (LOCK)
` Provides VGA/Palette Memory and I/O, and Subtractive Decoding Options, LED Activity Terminals
` Fully Interoperable with FireWire<sup>TM</sup> and i.LINK<sup>TM</sup> Implementations of IEEE Std 1394
` Compliant with Intel Mobile Power Guideline 2000
` Full IEEE Std 1394a-2000 Support Includes: Connection Debounce, Arbitrated Short Reset, Multispeed Concatenation,Arbitration Acceleration, Fly-By Concatenation, and Port Disable/Suspend/Resume
` Power-Down Features to Conserve Energy in Battery-Powered Applications Include:Automatic Device Power Down During Suspend, PCI Power Management for Link-Layer and Inactive Ports Powered Down, Ultralow-Power Sleep Mode
` Two IEEE Std 1394a-2000 Fully Compliant Cable Ports at 100M Bits/s, 200M Bits/s,and 400M Bits/s
` Cable Ports Monitor Line Conditions for Active Connection to Remote Node
` Cable Power Presence Monitoring
` Separate Cable Bias (TPBIAS) for Each Port
` Physical Write Posting of up to Three Outstanding Transactions
` PCI Burst Transfers and Deep FIFOs to Tolerate Large Host Latency
` External Cycle Timer Control for Customized Synchronization
` Extended Resume Signaling for Compatibility with Legacy DV Components
` PHY-Link Logic Performs System Initialization and Arbitration Functions
` PHY-Link Encode and Decode Functions Included for Data-Strobe Bit Level Encoding
` PHY-Link Incoming Data Resynchronized to Local Clock
` Low-Cost 24.576-MHz Crystal Provides Transmit and Receive Data at 100M Bits/s,200M Bits/s, and 400M Bits/s
` Node Power Class Information Signaling for System Power Management
` Register Bits Give Software Control of Contender Bit, Power Class Bits, Link Active Control Bit, and IEEE Std 1394a-2000 Features

Supply voltage range: VR_PORT . . . . −0.2 V to 2.2 V
ANALOGV_CC . . . . . . . . . . . . . . . . . . . . . −0.3 V to 4 V
V_CC . . . . . . . . . . . . . . . . . . . . . . . . . . .  −0.3 V to 4 V
PLLV_CC . . . . . . . . . . . . . . . . . . . . . . . . . −0.3 V to 4 V
V_CCCB . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 5.5 V
V_CCP . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 5.5 V
Clamping voltage range for V_CCP and V_CCCB . . .−0.5 to 6 V
Input voltage range for PCI, VI, CardBus, PHY, and Miscellaneous . . . −0.5 to V_CC + 0.5 V
Output voltage range for PCI, VO, CardBus, PHY, and Miscellaneous . .−0.5 to V_CC + 0.5 V
Input clamp current, I_IK (V_I < 0 or V_I > V_CC) (see Note 1) . . . . . .±20 mA
Output clamp current, I_OK (V_O < 0 or V_O > V_CC) (see Note 2) . . .±20 mA
Operating free-air temperature, T_A . . . .0°C to 70°C
Storage temperature range, T_stg . . −65°C to 150°C
Virtual junction temperature, T_J . . . . . . . .150°C
† Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating conditions is not implied.Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. Applies for external input and bidirectional buffers. V_I > V_CC does not apply to fail-safe terminals. PCI terminals and miscellaneous terminals are measured with respect to V_CCP instead of V_CC. PC Card terminals are measured with respect to V_CCCB. The limit specified applies for a dc condition.
2. Applies for external output and bidirectional buffers. V_O > V_CC does not apply to fail-safe terminals. PCI terminals and miscellaneous terminals are measured with respect to V_CCP instead of V_CC. PC Card terminals are measured with respect to V_CCCB. The limit specified applies for a dc condition.

The controller is compliant with PCI Local Bus Specification. Function 0 provides the independent PC Card socket controller compliant with the latest PC Card Standards. The controller provides features that make it the best choice for bridging between the PCI bus and PC Cards, and supports either 16-bit or CardBus PC Cards in the socket, powered at 5 V or 3.3 V, as required.

There are no PCMCIA card and socket service software changes required to move systems from the existing CardBus socket controller to the PCI4510R controller. The PCI4510R controller is register compatible with the Intel 82365SLDF ExCA controller and implements the host interface defined in the PC Card Standard.

The internal data path logic allows the host to access 8-, 16-, and 32-bit cards using full 32-bit PCI cycles for maximum performance. Independent buffering and the pipeline architecture provides an unsurpassed performance level with sustained bursting. The controller can be programmed to accept posted writes to improve bus utilization. All card signals are internally buffered to allow hot insertion and removal without external buffering.

Function 1 of the controller is an integrated IEEE 1394a-2000 open host controller interface (OHCI) PHY/link-layer controller (LLC) device that is fully compliant with the PCI Local Bus Specification, the PCI Bus Power Management Interface Specification, IEEE Std 1394-1995, IEEE Std 1394a-2000, and the 1394 Open Host Controller Interface Specification. It is capable of transferring data between the 33-MHz PCI bus and the 1394 bus at 100M bits/s, 200M bits/s, and 400M bits/s. The controller provides two 1394 ports that have separate cable bias (TPBIAS). The controller also supports the IEEE Std 1394a-2000 power-down features for battery-operated applications and arbitration enhancements.

As required by the 1394 Open Host Controller Interface Specification and IEEE Std 1394a-2000, internal control registers are memory-mapped and nonprefetchable. The PCI configuration header is accessed through configuration cycles specified by PCI, and it provides plug-and-play (PnP) compatibility. Furthermore,the controller is compliant with the PCI Bus Power Management Interface Specification as specified by the PC 2001 Design Guide requirements. The controller supports the D0, D1, D2, and D3 power states.

The controller provides PCI bus master bursting, and it is capable of transferring a cacheline of data at 132M bytes/s after connection to the memory controller. Because PCI latency can be large, deep FIFOs are provided to buffer the IEEE 1394 data.

The controller provides physical write posting buffers and a highly-tuned physical data path for SBP-2 performance. The controller also provides multiple isochronous contexts, multiple cacheline burst transfers,advanced internal arbitration, and bus-holding buffers.

The PHY-layer provides the digital and analog transceiver functions needed to implement a two-port node in a cable-based 1394 network. Each cable port incorporates two differential line transceivers. The transceivers include circuitry to monitor the line conditions as needed for determining connection status, for initialization and arbitration, and for packet reception and transmission.