PCI2031

Features: ·PCI Power Management Compliant·ACPI 1.0 Compliant·Supports PCI Local Bus Specification 2.1 and PCI-to-PCI Bridge Specification 1.0·3.3-V Core Logic With Universal PCI Interfaces Compatible With 3.3-V and 5-V PCI Signaling Environments·Supports Two 32-Bit, 33-MHz PCI Buses·Provides Inter...

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PCI2031 Picture
SeekIC No. : 004456580 Detail

PCI2031: Features: ·PCI Power Management Compliant·ACPI 1.0 Compliant·Supports PCI Local Bus Specification 2.1 and PCI-to-PCI Bridge Specification 1.0·3.3-V Core Logic With Universal PCI Interfaces Compatibl...

floor Price/Ceiling Price

Part Number:
PCI2031
Supply Ability:
5000

Price Break

  • Qty
  • 1~5000
  • Unit Price
  • Negotiable
  • Processing time
  • 15 Days
Total Cost: $ 0.00

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Upload time: 2024/11/13

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Product Details

Description



Features:

·PCI Power Management Compliant
·ACPI 1.0 Compliant
·Supports PCI Local Bus Specification 2.1 and PCI-to-PCI Bridge Specification 1.0
·3.3-V Core Logic With Universal PCI Interfaces Compatible With 3.3-V and 5-V PCI Signaling Environments
·Supports Two 32-Bit, 33-MHz PCI Buses
·Provides Internal Arbitration for Up to Six Secondary Bus Masters With Programmable Control
·Provides Six Secondary PCI Bus Clock Outputs
·Supports Burst Transfers to Maximize Data Throughput on Both PCI Buses
·Provides Two Extension Windows
·EEPROM Interface for Loading Texas Instruments (TIE) Subsystem ID and Subsystem Vendor ID
·Four Primary and Four Secondary General-Purpose I/Os
·Secondary Positive Decode
·Independent Read and Write Buffers for Each Direction
·Predictable Latency: Compliant With PCI Local Bus Specification 2.1
·External Arbiter Option
·Provides Concurrent Operation
·Serial IRQ Bridging
·Propagates Bus Locking
·Supports PCI Clock Run
·Secondary Bus Driven Low During Reset
·Docking Connect Detects
·PCI Local Bus Specification 2.0-Compliant Device Optimization
·Advanced Submicron, Low-Power CMOS Technology
·Provides VGA/Palette Memory and I/O, and Subtractive Decoding Options
·Packaged in 176-Pin Plastic Quad Flatpack



Pinout

  Connection Diagram


Specifications

Supply voltage range: VCC . . . . . . . . . . . . . . . . . . . . . .0.5 V to 4.6 V
VCCP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.5 V to 6 V
Input voltage range, VI: Standard . . . . . . . . . . .0.5 V to VCC + 0.5 V
Output voltage range, VO: Standard . . . . . . . . 0.5 V to VCC + 0.5 V
Input clamp current, IIK (VI < 0 or VI > VCC) (see Note 1) . . . ±20 mA
Output clamp current, IOK (VO < 0 or VO > VCC) (see Note 2) . ±20 mA
Storage temperature range, Tstg . . . . . . . . . . . . . . . . . 65°C to 150°C
Virtual junction temperature, TJ . . . . . . . . . . . . . . . . . . . . . . . . . 150°C



Description

The TI PCI2031 PCI-to-PCI bridge provides a high-performance connection path between two peripheral component interconnect (PCI) buses. Transactions can occur between a master on one PCI bus and a target on another PCI bus. The bridge PCI2031 supports burst-mode transfers to maximize data throughput, and the two bus traffic paths through the bridge act independently.

The PCI2031 bridge is compliant with the PCI Local Bus Specification 2.1, and can be used to overcome the electrical loading limit of ten devices per PCI bus by creating hierarchical buses. Furthermore, add-in cards requiring multiple PCI devices of PCI2031 can use the bridge to overcome the electrical loading limit of one PCI device per slot.

The PCI2031 bridge is also compliant with the PCI-to-PCI Bridge Specification 1.0, and implements many additional features that make it an ideal solution for bridging two PCI buses. PCI2031 can be configured for subtractive decoding, and negative decoding can be disabled on the secondary interface. Two extension windows of PCI2031 are also included for special decoding purposes. The serial- and parallel-port addresses can also be programmed for positive decoding on the primary interface. The bridge implements many other features, listed above, that add performance and flexibility.

An advanced CMOS PCI2031 process is utilized to achieve low system-power consumption while operating at PCI clock rates up to 33 MHz.




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