Features: ` Implements the MIL-STD-1750A Instruction Set` Architecture` Single Chip PACE TechnologyTM CMOS 16-Bit` Processor with 32 and 48-Bit Floating Point Arithmetic` DAIS Instruction Mix Execution Performance` Including Floating Point Arithmetic 1.3 MIPS at 20 MHz 1.9 MIPS at 30 MHz 2.6 MIPS ...
PACE1750A: Features: ` Implements the MIL-STD-1750A Instruction Set` Architecture` Single Chip PACE TechnologyTM CMOS 16-Bit` Processor with 32 and 48-Bit Floating Point Arithmetic` DAIS Instruction Mix Execut...
SeekIC Buyer Protection PLUS - newly updated for 2013!
268 Transactions
All payment methods are secure and covered by SeekIC Buyer Protection PLUS.
Features: ` Implements the MIL-STD-1750A Instruction Set` Architecture` ` Single Chip PACE Technol...
Supply Voltage Range | 0.5V to +7.0V |
Input Voltage Range | 0.5V to VCC + 0.5V |
Storage Temperature Range | 65°C to +150°C |
Input Current Range | 30mA to +5mA |
Current applied to any output3 | 150mA |
Maximum Power Dissipation2 | 1.5W |
Lead Temperature Range (soldering 10 seconds) |
300°C |
The PACE1750A is a general purpose, single chip, 16-bit CMOS microprocessor designed for high performance floating point and integer arithmetic, with extensive real time environment support. PACE1750A offers a variety of data types, including bits, bytes, 16-bit and 32-bit integers, and 32-bit and 48-bit floating point numbers. It provides 13 addressing modes, including direct, indirect, indexed, based, based indexed and immediate long and short, and PACE1750A can access 2 MWords of segmented memory space (64 KWords segments).
The PACE1750A offers a well-rounded instruction set with 130 instruction types, including a comprehensive integer, floating point, integer-to-floating point and floating point-to-integer set, a variety of stack manipulation instructions, high level language support instructions such as Compare Between Bounds and Loop Control Instructions. PACE1750A also offers some unique instructions such as vectored l/O, supports executive and user modes, and provides an escape mechanism which allows user-defined instructions using a coprocessor.
PACE1750A includes 16 general purpose registers, 8 other user-accessible registers, and an array of real time application support resources, such as 2 programmable timers of PACE1750A, a complete interrupt controller supporting 16 levels of prioritized internal and external interrupts, and a faults and exceptions handler controlling internally and externally generated faults.
The microprocessor achieves very high throughput of 2.6 MIPS for a standard real time integer/floating point instruction mix at a 40 MHz clock. PACE1750A executes integer Add in 0.1 s, integer Multiply in 0.575 s, Floating Point Add in 0.7 s, and Floating Point Multiply in 1.075 s, for register operands at a 40 MHz clock speed.
The PACE1750A uses a single multiplexed 16-bit parallel bus. Status signals are provided to determine whether the processor is in the memory or I/O bus cycle, reading and writing, and whether the bus cycle is for data or instructions.
The basic bus cycle is 4 clocks long. The PACE1750A will extend the cycle by insertion of wait states in the address and data phases (in response to RDYA and RDYD signals, repectively) and PACE1750A will hold the machine in HI-Z if this CPU PACE1750A has not acquired the bus. A typical non-bus cycle is three clocks long. However, variable length cycles are used for such repetitive operations as multiply, divide, scale and normalize, reducing significantly the number of CPU CLOCKS per operation step and resulting in very fast integer and floating point execution times.