Features: ITEM P2V28S20/30/40ATP -7 -75 -8 tCLK Clock Cycle Time (Min.) CL=2 - 10ns 10ns CL=3 7ns 7.5ns 8ns tRAS Active to Precharge Command Period (Min.) 45ns 45ns 48ns tRCD Row to Column Delay (Min.) 20ns 20ns 20ns tA...
P2V28S40ATP-7: Features: ITEM P2V28S20/30/40ATP -7 -75 -8 tCLK Clock Cycle Time (Min.) CL=2 - 10ns 10ns CL=3 7ns 7.5ns 8ns tRAS Active to Precharge Command Per...
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ITEM |
P2V28S20/30/40ATP | ||||
-7 |
-75 |
-8 | |||
tCLK | Clock Cycle Time (Min.) |
CL=2 |
- |
10ns |
10ns |
CL=3 |
7ns |
7.5ns |
8ns | ||
tRAS | Active to Precharge Command Period (Min.) |
45ns |
45ns |
48ns | |
tRCD | Row to Column Delay (Min.) |
20ns |
20ns |
20ns | |
tAC | Access Time from CLK (Max.) |
CL=2 |
- |
6ns |
6ns |
CL=3 |
5.4ns |
5.4ns |
6ns | ||
tRC | Ref /Active Command Period (Min.) |
63ns |
67.5ns |
70ns | |
Icc1 | Operation Current (Single Bank) (Max.) |
V28S20D |
85mA |
85mA |
85mA |
V28S30D |
85mA |
85mA |
85mA | ||
V28S40D |
85mA |
85mA |
85mA | ||
Icc6 | Self Refresh Current (Max.) |
-7,-75,-8 |
1mA |
1mA |
1mA |
Symbol |
Parameter |
Conditions |
Ratings |
Unit |
Vdd |
Supply Voltage |
with respect to Vss |
-0.5 - 4.6 |
V |
VddQ |
Supply Voltage for Output |
with respect to VssQ |
-0.5 - 4.6 |
V |
VI |
Input Voltage |
with respect to Vss |
-0.5 - 4.6 |
V |
VO |
Output Voltage |
with respect to VssQ |
-0.5 - 4.6 |
V |
IO |
Output Current |
50 |
mA | |
Pd |
Power Dissipation |
Ta = 25°C |
1000 |
mW |
Topr |
Operating Temperature |
0 - 70 |
°C | |
Tstg |
Storage Temperature |
-65 - 150 |
°C |
P2V28S20ATP is organized as 4-bank x 8,388,608-word x 4-bit Synchronous DRAM with LVTTL interface and P2V28S30ATP is organized as 4-bank x 4,194,304-word x 8-bit and P2V28S40ATP is organized as 4-bank x 2,097, 152-word x 16-bit. All inputs and outputs are referenced to the rising edge of CLK.
P2V28S20ATP,P2V28S30ATP and P2V28S40ATP achieve very high speed data rates up to 166MHz, and are suitable for main memories or graphic memories in computer systems.