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P2V28S20ATP-75

Features: ITEM P2V28S20/30/40ATP -7 -75 -8 tCLK Clock Cycle Time (Min.) CL=2 - 10ns 10ns CL=3 7ns 7.5ns 8ns tRAS Active to Precharge Command Period (Min.) 45ns 45ns 48ns tRCD Row to Column Delay (Min.) 20ns 20ns 20ns tA...

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SeekIC No. : 004439151 Detail

P2V28S20ATP-75: Features: ITEM P2V28S20/30/40ATP -7 -75 -8 tCLK Clock Cycle Time (Min.) CL=2 - 10ns 10ns CL=3 7ns 7.5ns 8ns tRAS Active to Precharge Command Per...

P2V28S20ATP-75 Data Sheet

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Part Number:
P2V28S20ATP-75
Supply Ability:
5000

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  • Qty
  • 1~5000
  • Unit Price
  • Negotiable
  • Processing time
  • 15 Days
Total Cost: $ 0.00

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Product Details

Description



Features:

ITEM
P2V28S20/30/40ATP
-7
-75
-8
tCLK Clock Cycle Time (Min.)
CL=2
-
10ns
10ns
CL=3
7ns
7.5ns
8ns
tRAS Active to Precharge Command Period (Min.)
45ns
45ns
48ns
tRCD Row to Column Delay (Min.)
20ns
20ns
20ns
tAC Access Time from CLK (Max.)
CL=2
-
6ns
6ns
CL=3
5.4ns
5.4ns
6ns
tRC Ref /Active Command Period (Min.)
63ns
67.5ns
70ns
Icc1 Operation Current (Single Bank) (Max.)
V28S20D
85mA
85mA
85mA
V28S30D
85mA
85mA
85mA
V28S40D
85mA
85mA
85mA
Icc6 Self Refresh Current (Max.)
-7,-75,-8
1mA
1mA
1mA
- Single 3.3V ±0.3V power supply
- Max. Clock frequency -7:143MHz<3-3-3>/-75:133MHz<3-3-3>/-8:100MHz<2-2-2>
- Fully synchronous operation referenced to clock rising edge
- 4-bank operation controlled by BA0,BA1(Bank Address)
- /CAS latency- 2/3 (programmable)
- Burst length- 1/2/4/8/FP (programmable)
- Burst type- Sequential and interleave burst (programmable)
- Byte Control- DQML and DQMU (P2V28S40ATP)
- Random column access
- Auto precharge / All bank precharge controlled by A10
- Auto and self refresh
- 4096 refresh cycles /64ms
- LVTTL Interface
- Package
P2V28S20ATP/30ATP/40ATP
400-mil, 54-pin Thin Small Outline (TSOP II) with 0.8mm lead pitch


Pinout

Connection Diagram


Specifications

Symbol
 Parameter
Conditions
Ratings
Unit
Vdd
 Supply Voltage
with respect to Vss
-0.5 - 4.6
V
VddQ
 Supply Voltage for Output
with respect to VssQ
-0.5 - 4.6
V
VI
 Input Voltage
with respect to Vss
-0.5 - 4.6
V
VO
 Output Voltage
with respect to VssQ
-0.5 - 4.6
V
IO
 Output Current
50
mA
Pd
 Power Dissipation
Ta = 25°C
1000
mW
Topr
 Operating Temperature
0 - 70
°C
Tstg
 Storage Temperature
-65 - 150
°C



Description

P2V28S20ATP is organized as 4-bank x 8,388,608-word x 4-bit Synchronous DRAM with LVTTL interface and P2V28S30ATP is organized as 4-bank x 4,194,304-word x 8-bit and P2V28S40ATP is organized as 4-bank x 2,097, 152-word x 16-bit. All inputs and outputs are referenced to the rising edge of CLK.

P2V28S20ATP,P2V28S30ATP and P2V28S40ATP achieve very high speed data rates up to 166MHz, and are suitable for main memories or graphic memories in computer systems.




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