NTE849

The NTE849 is an integrated circuit in a 14Lead DIP type package designed for use in TV horizontal/vetical countdown digital sync systems.  In some video playback units, there are incorrect frequency relationships between horizontal and field frequencies.  Automatic forced asynchronous mode of NTE849 eliminates jitter when equalizer pulses are correct, but these incorrect frequency relationships exist.

Automatic standard mode of NTE849 occurs upon detection of nine or more equalizing pulses during a sixlinewidth vertical driving period after seven fields of coincidence between integrated vertical (IV) sync and internal counter output.  Standard mode is retained for seven fields of missing or mutilated vertical sync pulses.

If two or more noise pulses of NTE849 are detected at Pin12 during a 384line active scan time, a noise detector reverts the system to standard mode at the next field of coincidence (without seven fields of coinci- dene delay). Thus, the unit stays in standard mode during tuner channel changes.

An automatic moderecognition system of NTE849 places the unit in standard mode for NTSC signals or into nonsynchronous mode for nonstandard sync signals.

An external oscillator (NTE701) of NTE849 supplies an input to Pin9 that is 32 times the horizontal rate.  An inter-nal divideby16 counter converts this input (32fH) to 2fH for use elsewhere.  This 32fH signal is further divided to fH, which is available at Pin11 to drive the horizontal deflection circuits.  A divideby525 counter further divides the 2f_H signal to generate the vertical ramp generator timing pulses and the vertical blanking pulse.

An automatic moderecognition system of NTE849 places the unit in standard mode for NTSC signals or into nonsynchronous mode for nonstandard sync signals.

An external oscillator (NTE701) of NTE849 supplies an input to Pin9 that is 32 times the horizontal rate.  An inter-nal divideby16 counter converts this input (32fH) to 2fH for use elsewhere.  This 32fH signal is further divided to fH, which is available at Pin11 to drive the horizontal deflection circuits.  A divideby525 counter further divides the 2fH signal to generate the vertical ramp generator timing pulses and the vertical blanking pulse.

A phasing circuit (part of the mode recognition and vertical regeneration circuits) of NTE849 insures that the 525 counter is reset in coincidence with the vertical sync.  It does this by comparing the internally gener-ated vertical pulse with an extrnal integrated vertical sync signal applied to Pin12.  The automatic mode recognition circuit forces the NTE849 into the standard mode for NTSC signals or into the nonsynchronous mode for nonstandard sync signals such as video games.  An input control signal (or no connection) at Pin8 places the NTE849 into non synchronous operation.

A phasing and timing logic circuit of NTE849 checks to see if the line counter is in sync with the IV signal at Pin12.Seven consecutive fields of inphase coincidence with the IV signal are needed to achieve standard mode in unless two or more noise pulses are dedetected at input Pin12 during the active scan time. In this case, normal mode will be acquired in one field.