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NM24C65

Features: ` Extended operating voltage 2.7V 5.5V` 400 KHz clock frequency (F) at 2.7V - 5.5V` 200mA active current typical 10mA standby current typical 1mA standby typical (L) 0.1mA standby typical (LZ)` IIC compatible interface Provides bidirectional data transfer protocol` 32 byte page write m...

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SeekIC No. : 004434840 Detail

NM24C65: Features: ` Extended operating voltage 2.7V 5.5V` 400 KHz clock frequency (F) at 2.7V - 5.5V` 200mA active current typical 10mA standby current typical 1mA standby typical (L) 0.1mA standby typical...

NM24C65 Data Sheet

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Part Number:
NM24C65
Supply Ability:
5000

Price Break

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  • 1~5000
  • Unit Price
  • Negotiable
  • Processing time
  • 15 Days
Total Cost: $ 0.00

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Product Details

Description



Features:

` Extended operating voltage 2.7V 5.5V
` 400 KHz clock frequency (F) at 2.7V - 5.5V
` 200mA active current typical
    10mA standby current typical
    1mA standby typical (L)
    0.1mA standby typical (LZ)
` IIC compatible interface
    Provides bidirectional data transfer protocol
` 32 byte page write mode
    Minimizes total write time per byte
` Self timed write cycle Typical write cycle time of 6ms
` Hardware write protect for upper block
` Endurance: 1,000,000 data changes
` Data retention greater than 40 years
` Packages available: 8-pin SO, 8-pin DIP
` Low VCC programming lockout (3.8V - on Standard VCC devices only).

 




Pinout

Connection Diagram


Specifications

Ambient Storage Temperature  . . . .65°C to +150°C
All Input or Output Voltages
with Respect to Ground 6.5V to  . . . . . . . . . . . . . 0.3V
Lead Temperature
(Soldering, 10 seconds)  . . . . . . . . . . . . . . . . ..+300°C
ESD Rating  . . . . . . . . . . . . . . . . . . . . . . . . . .2000V min.


Description

The NM24C65 devices are 65,536 bits of CMOS nonvolatile electrically erasable memory. NM24C65 offer the designer different low voltage and low power options, and they conform to all in the Extended IIC 2-wire protocol. Furthermore, they are designed to minimize device pin count and simplify PC board layout requirements.

The upper half of the memory of NM24C65 can be disabled (Write Protection) by connecting the WP pin to VCC. This section of memory then becomes ROM.

This communication protocol of NM24C65 uses CLOCK (SCL) and DATA I/O (SDA) lines to synchronously clock data between the master (for example a microprocessor) and the slave EEPROM device(s).

Fairchild EEPROMs are designed and tested for applications requiring high endurance, high reliability, and low power consumption.




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