Features: • Maximum Input Clock Frequency > 7 GHz Typical• Maximum Input Data Rate > 7 Gb/s Typical• 200 ps Typical Propagation Delay (OLS = FLOAT)• 55/45 ps Typical Rise/Fall Times (OLS = FLOAT)• Selectable Swing PECL Output with Operating Range:VCC = 2.375 V t...
NBSG72A: Features: • Maximum Input Clock Frequency > 7 GHz Typical• Maximum Input Data Rate > 7 Gb/s Typical• 200 ps Typical Propagation Delay (OLS = FLOAT)• 55/45 ps Typical Ri...
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Symbol |
Parameter | Condition 1 | Condition 2 |
Rating |
Units |
VCC |
Positive Power Supply | VEE = 0 V |
3.6 |
V | |
VEE |
Negative Power Supply | VCC = 0 V |
-3.6 |
V | |
VI |
Positive Input Negative Input |
VEE = 0 V VCC = 0 V |
VI VCC VI VEE |
3.6 -3.6 |
V V |
VINPP |
Differential Input Voltage |DX - DX | | VCC - VEE 2.8 V VCC - VEE < 2.8 V |
2.8 |VCC - VEE| |
V V | |
Iout |
Output Current | Continuous Surge |
25 50 |
mA mA | |
IIN |
Input Current Through RT (50 Resistor) | Static Surge |
80 |
mA | |
TA |
Operating Temperature Range |
-40 to +85 |
|||
Tstg |
Storage Temperature Range |
-65 to +150 |
|||
JA |
Thermal Resistance (Junction-to-Ambient) (Note 2) |
0 LFPM 500 LFPM |
QFN−16 QFN−16 |
42 35 |
/W /W /W /W |
JC |
Thermal Resistance (Junction-to-Case) | (Note 2) | QFN−16 |
4 |
/W |
Tsol |
Wave Solder | < 15 Sec |
225 |
Maximum ratings are those values beyond which device damage can occur. Maximum ratings applied to the device are individual stress limit values (not normal operating conditions) and are not valid simultaneously. If these limits are exceeded, device unctional operation is not implied, damage may occur and reliability may be affected.
2. JEDEC standard multilayer board − 1S2P (1 signal, 2 power).
The NBSG72A is a high−bandwidth fully differential 2 X 2 crosspoint switch with Output Level Select (OLS) capabilities. This is a part of the GigaComm] family of high performance Silicon Germanium products. The NBSG72A is housed in a low profile 3 X 3 mm 16−pin QFN package. Differential inputs incorporate internal 50 termination resistors and accept NECL (Negative ECL), PECL (Positive ECL), LVCMOS/LVTTL, CML, or LVDS. The OLS input is used to program the peak−to−peak output amplitude between 0 mV and 800 mV in five discrete steps. The SELECT inputs are single−ended and can be driven with either LVECL or LVCMOS/LVTTL input levels.