NBSG53A

Maximum ratings are those values beyond which device damage can occur. Maximum ratings applied to the device are  ndividual stress limit values (not normal operating conditions) and are not valid simultaneously. If these limits are exceeded, device  unctional operation is not implied, damage may occur and reliability may be affected.
6. JEDEC standard 51−6, multilayer board − 2S2P (2 signal, 2 power).
7. JEDEC standard multilayer board − 2S2P (2 signal, 2 power) with 8 filled thermal vias under exposed pad.

The NBSG53A is a multi−function differential D flip−flop (DFF) or fixed divide by two (DIV/2) clock generator. This is a part of the GigaComm] family of high performance Silicon Germanium products. A strappable control pin is provided to select between the two functions. The device is housed in a low profile 4x4 mm 16−pin Flip−Chip BGA (FCBGA) or a 3x3 mm 16 pin QFN package.

The NBSG53A is a device with data, clock, OLS, reset, and select inputs. Differential inputs incorporate internal 50
 termination resistors and accept NECL (Negative ECL), PECL (Positive ECL), LVCMOS/LVTTL, CML, or LVDS. The OLS input is used to program the peak−to−peak output amplitude between 0 and 800 mV in five discrete steps. The RESET and SELECT inputs are single−ended and can be driven with either LVECL or LVCMOS/LVTTL input levels.

Data is transferred to the outputs on the positive edge of the clock. The differential clock inputs of the NBSG53A allow the device to also be used as a negative edge triggered device.