Features: • Maximum Input Clock Frequency > 10 GHz Typical• Maximum Input Data Rate > 10 Gb/s Typical• 120 ps Typical Propagation Delay• 35 ps Typical Rise and Fall Times• Positive CML Output with Operating Range: VCC = 2.375 V to 3.465 V with VEE = 0 V• N...
NBSG16M: Features: • Maximum Input Clock Frequency > 10 GHz Typical• Maximum Input Data Rate > 10 Gb/s Typical• 120 ps Typical Propagation Delay• 35 ps Typical Rise and Fall Tim...
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Symbol |
Parameter |
Condition 1 | Condition 2 |
Rating |
Units |
VCC |
LVPECL Power Supply | VEE = 0 V |
3.6 |
V | |
VEE |
NECL Power Supply | VCC = 0 V |
-3.6 |
V | |
VI |
Positive Input Negative Input |
VEE = 0 V VCC = 0 V |
VI VCC VI VEE |
3.6 -3.6 |
V V |
VINPP |
Differential Input Voltage |D-D| | VCC - VEE 2.8 VCC - VEE < 2.8 |
2.8 |VCC-VEE| |
V | |
IIN |
Input Current Through RT (50 Resistor) | Static Surge |
45 80 |
V V | |
Iout |
Output Current | Continuous Surge |
25 50 |
mA mA | |
IBB |
VBB Sink/Source | ||||
TA |
Operating Temperature Range |
-40 to +85 |
|||
Tstg |
Storage Temperature Range |
-65 to +150 |
|||
JA |
Thermal Resistance (Junction-to-Ambient) (Note5) |
0 LFPM 500 LFPM |
QFN−16 QFN−16 |
42 35 |
/W /W |
JC |
Thermal Resistance (Junction-to-Case) | 1S2P (Note 5) |
QFN−16 |
4.0 |
/W |
Tsol |
Wave Solder | < 15 Sec |
225 |
Maximum ratings are those values beyond which device damage can occur. Maximum ratings applied to the device are ndividual stress limit values (not normal operating conditions) and are not valid simultaneously. If these limits are exceeded, device unctional operation is not implied, damage may occur and reliability may be affected.
5. JEDEC standard multilayer board − 1S2P (1 signal, 2 power)
Buffer NBSG16M is a differential current mode logic (CML) receiver/driver/translator buffer. The NBSG16M is functionally equivalent to the EP16, LVEP16, or SG16 devices with CML output structure and lower EMI capabilities.
Inputs incorporate internal 50 termination resistors and accept LVNECL (Negative ECL), LVPECL (Positive ECL), LVTTL, LVCMOS, CML, or LVDS. The CML output structure contains internal 50 source termination resistor to VCC. The NBSG16M generates 400 mV output amplitude with 50 receiver resistor to VCC.
The VBB pin of NBSG16M is internally generated voltage supply available to this device only. For all single−ended input conditions, the unused complementary differential input is connected to VBB as a switching reference voltage. VBB may also rebias AC coupled inputs. When used, decouple VBB via a 0.01 F capacitor and limit current sourcing or sinking to 0.5 mA. When not used, VBB output should be left open.