Features: * 2-port MAC bridge supports both Fast Ethernet and Ethernet/Fast Ethernet bridging* Minimum 16K byte, maximum 256K byte buffer memory* Selectable TX/FX/T4 symbol-level repeater, MII interfaces, and 10BASE serial port* T4 symbol mode includes the implementation of all PCS layers function...
MX98742: Features: * 2-port MAC bridge supports both Fast Ethernet and Ethernet/Fast Ethernet bridging* Minimum 16K byte, maximum 256K byte buffer memory* Selectable TX/FX/T4 symbol-level repeater, MII inter...
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RATING |
VALUE |
Supply Voltage (VCC) |
4.75V to 5.25V |
DC Input Voltage (Vin) |
-0.5V to VCC+ 0.5V |
DC Output Voltage (Vout) | -0.5V to VCC+ 0.5V |
Storage Temperature Range (TSTG) |
-55 C to 150 C |
Power Dissipation (PD) | 375 mW |
ESD rating (Rzap = 1.5K, Czap = 100pF) |
2000V |
Ambient Operating Temp |
0 C to 70 C |
Note:
1. Stress greater than those listed under Absolute Maximum Ratings may cause pemanent damage to the device.This is stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification are not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.
2. Preliminary, subject to change.
The MX98742 (FEBC) is a low-cost solution to link fast Ethernet repeaters together so that the distance between nodes can be expanded far beyond the 200m collision domain limitation. Each network segment connected through the bridge is in a separate collision domain, and the FEBC's function is to exchange all the good packets between two collision domain segments. A 512-bit hash filter is implemented to further reduce the traffic
between segments if it is desired. A 10/100 bridge function is also supported.
The MX98742 has two forwarding modes: (1) store-and forward : a complete packet is buffered before it is to be forwarded.Packets with CRC errors and other anomalies are discarded. (2) 64-byte forward : a packet is forwarded after the first 64 bytes are buffered. The number of bridges that can be put in one network is constrained largely by the buffer memory and performance consideration. Multiple FEBCs are totally invisible to the upper layer protocol.
The MX98742 supports direct TX PHY interface and 25MHz-MII on both side. Port A of the FEBC also supports TX and T4 repeater ports at the symbobl level and port B of the FEBC also supports the 7-wire serial 10 MHz interface. TheFEBC supports buffer memory from minimum 16 Kbytes to 256 Kbytes. The memory is partitioned into two sections with section A as the receive buffer for port A and section B for port B. The size of each section is equal if both sides are operating at 100 Mbps speed; the minimum size of each section is 8 Kbytes. In the auto-sizing mode, the FEBC will change the buffer size according to traffic pattern in each segment.