MX98205

• Provide single-chip controller of switching function among 4 10/100Mbps Full/Half-duplex Ethernet ports at wire speed.
• Support "Store-and-Forward" and "Cut-Through"switching scheme
• Support 1.0GBps (@66MHz) expansion (inter-switch) bus interface.
• Support source/destination address lookup, learning,and aging.
• Support IEEE802.3x flow control for FDX and backpressure flow control for HDX.
• Support up to 2MB sync. SRAM interface.
• Integrate 4 10/100MBps MAC controllers.
• Cascade 2 switch controllers to construct 8 10/100MBps switched Ethernet ports in a box easily without extra logic.
• 208-pin PQFP.

The MX98205 is a 4-port 10/100MBps single-chip shared-memory Ethernet switch controller. A desktop or segment switched Ethernet solution can be achieved by combining MX98205, the necessary physical interfaces and low-cost memory. All 4 ports are full-duplex capable to provide private 20/200MBps bandwidth connection to power users or servers through external physical (PHY) layers. System manufacturers can cascade 2 MX98205 switch controllers to build an 8-port 10/100MBps switched Ethernet box without extra logic.

The operation of MX98205 is as following. Data frame received from MII interface is buffered in Rx FIFO before being transferred to external packet buffers under control of queue manager (QM). Priority-based arbitration is utilized in QM to maintain memory I/O bandwidth and fast data transfer without contention. The address information of incoming frame, namely source address (SA) and destination address (DA), is extracted for address self-learning and determining the forwarding port.MX98205 builds the filtering database (or called address table) within external memory. Via hashing method, the new SA is verified and a new address entry of MAC and physical port I.D. mapping pair is recorded in address table. Same hash transformation is applied to DA to search the address table for determining forwarding port.If DAs of received frames are not recognized through address table, the frames would be forwarded to all other ports. Aging is provided to prevent address table from being overridden. Aging mechanism checks entries in the database to discard the least used ones. When the forwarding port is found, received frames is relayed to destination host through either Store-and-Forward or Cut-Through switching scheme. The switching scheme depends on the output buffer status of destination port.If the output buffer is empty and DA of received frame is recognized, Cut-through scheme is applied. But mostly there are frames queued in output buffer, Store-and-Forward scheme is applied.

Contention occurs if frames from different source hosts are forwarded to the same destination host simultaneously.Contention makes multiple frames be queued in data buffers. The flow control mechanism is built to prevent buffer overflow which forces controller to lose packets. MX98205 sets some water marks on output/input queue per port to justify the fullness of data buffers.As soon as buffer fullness is over the warning threshold,flow control mechanism is triggered to stop the respondent host(s) to transmit frames for sometime. For half-duplex operation MII(s), the jam pattern is issued to host. For full-duplex operation MII(s), specific "pause"frame of IEEE Std. 802.3x is issued to host. After buffer fullness drops below the safe threshold, controller releases flow control status to allow hosts to work in norm condition.

System manufactures' design flexibility is our concern too. MX98205 provides 8-bit width Tx bus, 8-bit width Uni-Rx bus and 8-bit width Broad-Rx bus associated with command line interface for system scalability. System manufacturers can cascade 2 MX98205s to make 8-port 10/100MBps switched Ethernet box without extra logic. Also system vendors can build 10/100Mbps dual-speed repeater with MX98205. In the application two of switch ports are connected by 10M segment and 100M segment separately for segment switch, other two switch ports could be used for uplink and server connection.