MX98726

MX98726 ( Generic MAC , or GMAC ) is a cost effective solution as a generic single chip 10/100 Fast Ethernet controller. It is designed to directly interface 80188, 80186 ( host ) without glue logic. Two types of memory sharing schemes are supported, i.e. interleaved and shared mode to support a variety of applications. Single chip solution will help reduce system cost not only on the components but also the board size. Full NWAY function with 10/100 tranceiver will ease the field installation, simply plug the chip in and it will connect itself with the best protocol available.

The interleaved mode allow uP to access SRAM ( packet/host buffer ) through MX98726's local DMA channel. This way, no extra SRAM interface logic is needed on the host side. If high performance is desired, then shared memory mode is another alternative which allow host to access SRAM on its own by denying SRAM busgrant to MX98726 using simple hand shake protocol.Without SRAM bus grant, MX98726 will float its interface connected to the SRAM, therefore host can utilize its own memory subsystem to conduct its own SRAM access.

A intelligent built-in SRAM bus arbitor will manage all the SRAM access requests from host, on-chip transmit channel and on-chip receive channel. The throughputof these network channels and MX98726's DMA burst length can be easily adjusted by option bits on the chip. These options can help system developers to "fine tune" a best cost/performance ratio.

MX98726 is also equipped with fast back-to-back transmit capability which allow software to "fire" as many transmit packets as needed in a single command. Receive FIFO also allow back-to-back reception. Optional EEPROM can be used to stored network network address and other information. In case cost is really a concern, most configuration options including network address can be programmed through uP.