Features: * Directly supports 32-bit fast PCI bus interface* Highly integrated with IEEE802.3 MAC and Nway in a single chip* Supports full-duplex operation for both 100Mbps and 10Mbps* Offers IEEE802.3u 100Mbps MII port supporting CAT3/CAT5 unshielded twisted-pair (UTP), shielded twisted-pair (STP...
MX98713: Features: * Directly supports 32-bit fast PCI bus interface* Highly integrated with IEEE802.3 MAC and Nway in a single chip* Supports full-duplex operation for both 100Mbps and 10Mbps* Offers IEEE80...
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The MX98713 PCI MAC ( PMAC ) device is an IEEE 802.3u Media Access Controller dedicated for PCI interface and is designed to ease interfacing with CSMA/CD type local area networks, including 100Mbps-TX/FX/T4 Fast Ethernet, 10Mbps Thick Ethernet, Thin Ehternet and StarLAN with external network transceivers and 10Mbps Twisted-pair Ethernet without external transceiver. High speed PCI bus master interface is implemented to support 100Mbps fast Ethernet with fast packet buffer management. On-chip control registers and PCI configuration registers provide interface to host system for automatic bus master configuration and driver controls. As a PCI bus master, PMAC incorporates large on-chip FIFOs which provide effective local packet buffers; therefore, no external local buffer memory is needed.
The MX98713 PMAC device implements all Media Access Control (MAC) layer functions for transmission and reception and Nway auto-negociation in accordance with the IEEE 802.3u standard. PMAC can be programmed to support various level of interconnects. Supported interconnects include standard Media Independent Interface(MII), 100BASE-TX Physical Coding Sublayer ( PCS ), NWAY Auto-negotiation for automatic speed selection and a direct 10BASE Twisted pair media interface.
The MX98713 can operate in full-duplex or half-duplex mode. A packet buffer is located in the host memory that is controlled by software driver for all incoming and outgoing packets. During reception, the PMAC stores packets in the receive buffer area, then indicates receiving status and control information in the descriptor area.This packet buffer is also used by transmission process which can transmit multiple packets from a single transmit command. Minimum-sized back-to-back packets at full line speed with interframe gap (IPG) of 0.96us in 100Mbps mode is effortless with the PMAC.