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MX98705

Features: • Complies with IEEE 802.3 Standards• Integral 10 Mb/s Buffer for Dual 10 Mb/s&100 Mb/s Applications• Baseline Wander correction• Adapative Equalization• 25 MHz to 125 MHz Transmit Clock Multiplier• Five Bit TTL Nibble at 25 MHz Input/Output•...

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SeekIC No. : 004431896 Detail

MX98705: Features: • Complies with IEEE 802.3 Standards• Integral 10 Mb/s Buffer for Dual 10 Mb/s&100 Mb/s Applications• Baseline Wander correction• Adapative Equalization• ...

MX98705 Data Sheet

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Part Number:
MX98705
Supply Ability:
5000

Price Break

  • Qty
  • 1~5000
  • Unit Price
  • Negotiable
  • Processing time
  • 15 Days
Total Cost: $ 0.00

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Upload time: 2024/11/26

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Product Details

Description



Features:

• Complies with IEEE 802.3 Standards
• Integral 10 Mb/s Buffer for Dual 10 Mb/s&100 Mb/s Applications
• Baseline Wander correction
• Adapative Equalization
• 25 MHz to 125 MHz Transmit Clock Multiplier
• Five Bit TTL Nibble at 25 MHz Input/Output
• 25 MHz received recovery clock
• Operates over 100 Meters of STP and Category 5 UTP Cable (>7.5 dB)
• Single +5V Supply
• 52 PQFP package


Pinout

Connection Diagram


Specifications

Vcc Supply Voltage Range ........................ -0.3V to 6V
Storage Temperatur ....................... -65°C to 150°C
Input Voltage Range
Lead Temperature (10 sec) .............................. 60°C
Digital Inputs .......................................... -0.3V to Vcc
ESD ............................................................ 2k VHHBM
Output Current
TXOP, TXON ...................................................... 70mA
All other outputs ............................................... 10mA


Description

The MX98705 is a fully intergrated physical layer device supporting 100Base-TX or FDDI over copper applications.The MX98705 integrates 125 MHz clock recovery/generation,receive adaptive equalization, and baseline wander correction, it provides 5-bit parallel interface to any MAC controller.

The MX98705 receive section includes an adaptive equalizer with DC baseline wander compensation, MLT-3 to NRZ decoder, and a 125 MHz receive clock recovery circuit. The transmit section provide NRZ to MLT-3 for 100Base-TX and a buffer for 10 Mb/s application.




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