Features: • Integrated Single-Chip 10/100/1000 Mbps Ethernet Switch
• 24 10/100 Mbps Autosensing, Fast Ethernet Ports with RMII or Serial Interface (7WS). Each port can independently use one of the two interfaces
• 2 Gigabit Ports with GMII, PCS, 10/100 and stacking (2 G per port) interface options per port
• Stacking port supports hot swap in managed configuration
• Supports 8/16-bit CPU interface in managed mode
• Serial interface in unmanaged mode
• Supports two Frame Buffer Memory domains with SRAM at 100 MHz
• Supports memory size 2 MB, or 4 MB
• For 24 + 2, two SRAM domains (2 MB or 4 MB) are required.
• For 24 + 2 stacking (2 G per stacking port), two ZBT domains (2 MB or 4 MB) are required
• Applies centralized shared memory architecture
• Up to 64 K MAC addresses
• Maximum throughput is 6.4 Gbps non-blocking
• High performance packet forwarding (19.047 M packets per second) at full wire speed
• Provides port based and ID tagged VLAN support (IEEE 802.1Q), up to 255 VLANs
• Supports IP Multicast with IGMP snooping
• Supports spanning tree with CPU, on per port or per VLAN basis
• Packet Filtering and Port Security
• Static address filtering for source and/or destination MAC
• Static MAC address not subject to aging
• Secure mode freezes MAC address learning Each port may independently use this mode
• Full Duplex Ethernet IEEE 802.3x Flow Control
• Backpressure flow control for Half Duplex ports
• Supports Ethernet multicasting and broadcasting and flooding control
• Supports per-system option to enable flow control for best effort frames even on QoSenabled portsSpecificationsStorage Temperature.................................................. -65 to +150
Operating Temperature .................................................-40 to +85
Maximum Junction Temperature ................................................+125
Supply Voltage VCC with Respect to VSS ....................+3.0 V to +3.6 V
Supply Voltage VDD with Respect to VSS ................+2.38 V to +2.75 V
Voltage on Input Pins ........................................-0.5 V to (VCC + 3.3 V)DescriptionThe MVTX2604 is a high density, low cost, high performance, non-blocking Ethernet switch chip. A single chip provides 24 ports at 10/100 Mbps, 2 ports at 1000 Mbps and a CPU interface for managed and unmanaged switch applications. The Gigabit ports can also support 10/100 M and 2 G stacking modes.
The chip supports up to 64 K MAC addresses and up to 255 port-based Virtual LANs (VLANs). The centralized shared memory architecture permits a very high performance packet forwarding rate at up to 9.524 M packets per second at full wire speed. The chip is optimized to provide low-cost, high-performance workgroup switching. Two Frame Buffer Memory domains utilize cost-effective, high-performance synchronous SRAM with aggregate bandwidth of 12.8 Gbps to support full wire speed on all ports simultaneously. In the 24+2 stacking (2 G per stacking port) configuration, 2 ZBT domains are needed.
With delay bounded, strict priority, and/or WFQ transmission scheduling, and WRED dropping schemes, the MVTX2604 provides powerful QoS functions for various multimedia and mission-critical applications. The chip provides 4 transmission priorities (8 priorities per Gigabit port) and 2 levels of dropping precedence. Each packet is assigned a transmission priority and dropping precedence based on the VLAN priority field in a VLAN tagged frame, or the DS/TOS field, or the UDP/TCP logical port fields in IP packets. The MVTX2604 recognizes a total of 16 UDP/TCP logical ports, 8 hard-wired and 8 programmable (including one programmable range).
The MVTX2604 supports 3 groups of port trunking/load sharing. One group is dedicated to the two Gigabit ports, and the other two groups to 10/100 ports, where each 10/100 group can contain up to 4 ports. Port trunking/load sharing can be used to group ports between interlinked switches to increase the effective network bandwidth. In half-duplex mode all ports support backpressure flow control to minimize the risk of losing data during long activity bursts. In full-duplex mode, IEEE 802.3x flow control is provided. The MVTX2604 also supports a persystem option to enable flow control for best effort frames, even on QoS-enabled ports.
The Physical Coding Sublayer (PCS) is integrated on-chip to provide a direct 10-bit interface for connection to SERDES chips. The PCS can be bypassed to provide a GMII interface.
Statistical information for SNMP and the Remote Monitoring Management Information Base (RMON MIB) are collected independently for all ports. Access to these statistical counters/registers is provided via the CPU interface. SNMP Management frames can be received and transmitted via the CPU interface creating a complete network management solution.
The MVTX2604 is fabricated using 0.25 micron technology. Inputs, however, are 3.3 V tolerant, and the outputs are capable of directly interfacing to LVTTL levels. The MVTX2604 is packaged in a 553-pin Ball Grid Array package.
MVTX2604 Data Sheet
