Features: • JEDEC-standard 168-pin, dual in-line memory module (DIMM)
• PC133- and PC100-compliant
• Registered inputs with one-clock delay
• Phase-lock loop (PLL) clock driver to reduce loading
• Utilizes 133 MHz and 125 MHz SDRAM components
• ECC-optimized pinout
• 64MB (8 Meg x 72) and 128MB (16 Meg x 72)
• Single +3.3V ±0.3V power supply
• Fully synchronous; all signals registered on positive edge of PLL clock
• Internal pipelined operation; column address can be changed every clock cycle
• Internal SDRAM banks for hiding row access/ precharge
• Programmable burst lengths: 1, 2, 4, 8, or full page
• Auto Precharge and Auto Refresh Modes
• Self Refresh Mode
• 64ms, 4,096-cycle refresh
• LVTTL-compatible inputs and outputs
• Serial Presence-Detect (SPD)SpecificationsVoltage on VDD Supply Relative to VSS . -1V to +4.6V
Voltage on Inputs, NC or I/O Pins
Relative to VSS ...................................... -1V to +4.6V
Operating Temperature, TA (ambient) ... 0°C to +70°C
Storage Temperature (plastic) .......... -55°C to +125°C
Power Dissipation ............................................... 18WDescriptionThe MT9LSDT872 and MT9LSDT1672 are high-speed CMOS, dynamic random-access, 64MB and 128MB memories organized in a x72 configuration. These modules use internally configured quad-bank SDRAMs with a synchronous interface (all signals are registered on the positive edge of clock signals CK0). Read and write accesses to the SDRAM modules MT9LSDT1672 are burst oriented; accesses start at a selected location and continue for a programmed number of locations in a programmed sequence. Accesses begin with the registration of an ACTIVE command, which is then followed by a READ or WRITE command. The address bits of MT9LSDT1672 registered coincident with the ACTIVE command are used to select the bank and row to be accessed (BA0, BA1 select the bank, A0-A11 select the row).
The address bits of MT9LSDT1672 registered coincident with the READ or WRITE command are used to select the starting column location for the burst access. These modules provide for programmable READ or WRITE burst lengths of 1, 2, 4, or 8 locations, or full page, with a burst terminate option. An auto precharge function may be enabled to provide a self-timed row precharge that is initiated at the end of the burst sequence. These modules MT9LSDT1672 use an internal pipelined architecture to achieve high-speed operation. This architecture is compatible with the 2n rule of prefetch architectures, but it also allows the column address to be changed on every clock cycle to achieve a high-speed, fully random access. Precharging one bank while accessing one of the other three banks will hide the PRECHARGE cycles and provide seamless, high-speed, random-access operation.
These modules MT9LSDT1672 are designed to operate in 3.3V, lowpower memory systems. An auto refresh mode is provided, along with a power-saving, power-down mode. All inputs and outputs are LVTTL-compatible. SDRAM modules offer substantial advances in DRAM operating performance, including the ability to synchronously burst data at a high data rate with automatic column-address generation, the ability to interleave between internal banks in order to hide precharge time, and the capability to randomly change column addresses on each clock cycle during a burst access. For more information regarding SDRAM operation, refer to the 64Mb and 128Mb SDRAM data sheets.
MT9LSDT1672 Data Sheet
