MT9LD272A(X)

Voltage on V_DD Pin Relative to V_SS ................. -1V to +4.6V
Voltage on Inputs or I/O Pins
Relative to V_SS ................................................ -1V to +4.6V
Operating Temperature, T_A (ambient) ......... 0°C to +70°C
Storage Temperature (plastic) ............... -55°C to +125°C
Power Dissipation .......................................................... 9W
*Stresses greater than those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only, and functional operation of the device at these or any other conditions above those indic ted in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.

The MT9LD272A(X) and  are randomly accessed 16MB and 32MB memories organized in a x72 configuration. They are specially processed to operate from 3V to 3.6V for low-voltage memory systems.

During READ or WRITE cycles, each bit of MT9LD272A(X) is uniquely  addressed through the 21/22 address bits, which are entered 11 bits (A0 -A10) at RAS# time and 10/11 bits (A0- A10) at CAS# time.

READ and WRITE cycles are selected with the WE# input. A logic HIGH on WE# dictates read mode, while a logic LOW on WE# dictates write mode. During a WRITE cycle, data-in (D) is latched by the falling edge of WE# or CAS#, whichever occurs last. An EARLY WRITE occurs when WE# is taken LOW prior to CAS# falling. A LATE WRITE or READ-MODIFY-WRITE of MT9LD272A(X) occurs when WE# falls after CAS# was taken LOW. During EARLY WRITE cycles, the data-outputs (Q) will remain High-Z regardless of the
state of OE#. During LATE WRITE or READ-MODIFYWRITE  cles, OE# must be taken HIGH to disable the dataoutputs prior to applying input data. If a LATE WRITE or READ-MODIFY-WRITE is attempted while keeping OE#, LOW, no WRITE will occur, and the data-outputs will drive read data from the accessed location.