MT58L64L32D

The Micron® SyncBurst™ SRAM family MT58L64L32D employs high- speed, low-power CMOS designs that are fabri-cated using an advanced CMOS process.

Micron's 2Mb SyncBurst SRAMs MT58L64L32D integrate a 128K x 18, 64K x 32, or 64K x 36 SRAM core with advanced synchronous peripheral circuitry and a 2-bit burst counter. All synchronous inputs pass through registerscontrolled by a positive-edge-triggered single clock input (CLK). The synchronous inputs of MT58L64L32D include all ad-
dresses, all data inputs, active LOW chip enable (CE#),two additional chip enables for easy depth expansion (CE2, CE2#), burst control inputs (ADSC#, ADSP#, ADV#), byte write enables (BWx#) and global write (GW#).

Asynchronous inputs of MT58L64L32D include the output enable (OE#), clock (CLK) and snooze enable (ZZ). There is also a burst mode pin (MODE) that selects between inter- leaved and linear burst modes. The data-out (Q), en-abled by OE#, is also asynchronous. WRITE cycles can be from one to two bytes wide (x18) or from one to four bytes wide (x32/x36), as controlled by the write control inputs.

Burst operation of MT58L64L32D can be initiated with either address status processor (ADSP#) or address status controller (ADSC#) input pins. Subsequent burst addresses can be internally generated as controlled by the burst advance pin (ADV#).

Address and write control of MT58L64L32D are registered on-chip to simplify WRITE cycles. This allows self-timed WRITE cycles. Individual byte enables allow individual bytes
to be written. During WRITE cycles on the x18 device, BWa# controls DQa pins and DQPa; BWb# controls DQb pins and DQPb. During WRITE cycles on the x32 and x36 devices, BWa# controls DQa pins and DQPa; BWb# controls DQb pins and DQPb; BWc# controls