Features: • Fast clock and OE# access times
• Single +3.3V +0.3V/-0.165V power supply (VDD)
• Separate +3.3V or +2.5V isolated output buffer supply (VDDQ)
• SNOOZE MODE for reduced-power standby
• Common data inputs and data outputs
• Individual BYTE WRITE control and GLOBAL WRITE
• Three chip enables for simple depth expansion and address pipelining
• Clock-controlled and registered addresses, data I/Os and control signals
• Internally self-timed WRITE cycle
• Burst control pin (interleaved or linear burst)
• Automatic power-down
• 100-pin TQFP package
• Low capacitive bus loading
• x18, x32, and x36 versions availablePinout
SpecificationsVoltage on VDD Supply
Relative to VSS ....................................-0.5V to +4.6V
Voltage on VDDQ Supply
Relative to VSS .................................... -0.5V to +4.6V
VIN ............................................ -0.5V to VDDQ + 0.5V
Storage Temperature (plastic) ....... -55°C to +150°C
Junction Temperature** ................................ +150°C
Short Circuit Output Current ........................... 100mA
*Stresses greater than those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only, and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.
**Maximum junction temperature depends upon package type, cycle time, loading, ambient temperature and airflow. See Micron Technical Note TN-05-14 for more information.
DescriptionThe Micron® SyncBurst™ SRAM family MT58L128L18F employs high-speed, low-power CMOS designs that are fabricated using an advanced CMOS process.
Micron's 2Mb SyncBurst SRAMs MT58L128L18F integrate a 128K x 18, 64K x 32, or 64K x 36 SRAM core with advanced synchronous peripheral circuitry and a 2-bit burst counter. All synchronous inputs pass through registers controlled by a positive-edge-triggered single clock input (CLK). The synchronous inputs of MT58L128L18F include all addresses, all data inputs, active LOW chip enable (CE#), two additional chip enables for easy depth expansion (CE2, CE2#), burst control inputs (ADSC#, ADSP#, ADV#), byte write enables (BWx#) and global write (GW#).
Asynchronous inputs of MT58L128L18F include the output enable (OE#), snooze enable (ZZ) and clock (CLK). There is also a burst mode pin (MODE) that selects between interleaved and linear burst modes. The data-out (Q), enabled by OE#, is also asynchronous. WRITE cycles can be from one to two bytes wide (x18) or from one to four bytes wide (x32/x36), as controlled by the write control inputs.
Burst operation of MT58L128L18F can be initiated with either address status processor (ADSP#) or address status controller (ADSC#) input pins. Subsequent burst addresses can be internally generated as controlled by the burst advance pin (ADV#).
MT58L128L18F, Data Sheet
